A 0.5-v 5.2-fj/conversion-step full asynchronous sar adc with leakage power reduction down to 650 pw by boosted self-power gating in 40-nm CMOS

Ryota Sekimoto, Akira Shikata, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro

Research output: Contribution to journalArticle

27 Citations (Scopus)

Abstract

This paper presents an ultralow-power and ultralow-voltage SAR ADC. Full asynchronous operation and boosted self-power gating are proposed to improve conversion accuracy and reduce static leakage power. By designing with MOSFET of high threshold voltage (rm HVt) and low threshold voltage (rm LVt), the leakage power is reduced without decrease of maximum sampling frequency. The test chip in 40-nm CMOS process has successfully reduced leakage power by 98%, and it achieves 8.2-bit ENOB and while consuming only 650 pW at 0.1 kS/s from 0.5-V power supply. The power consumption is scalable up to 4 MS/s and power supply range from 0.4 to 0.7 V. The best figure of merit at 0.5 V is 5.2 fJ/conversion-step at 20 kS/s.

Original languageEnglish
Article number6578607
Pages (from-to)2628-2636
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Volume48
Issue number11
DOIs
Publication statusPublished - 2013

Keywords

  • Asynchronous
  • Data converter
  • Leakage power
  • Low-power
  • Low-voltage
  • Power gating
  • Successive-approximation-register (SAR) ADC

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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