A 0.55 V 10 fJ/bit inductive-coupling data link and 0.7 V 135 fJ/cycle clock link with dual-coil transmission scheme

Noriyuki Miura, Tsunaaki Shidei, Yuxiang Yuan, Shusuke Kawai, Keita Takatsu, Yuji Kiyota, Yuichi Asano, Tadahiro Kuroda

Research output: Contribution to journalArticle

15 Citations (Scopus)

Abstract

This paper presents a 10 fJ/bit inductive-coupling data link operating at 0.55 V supply voltage and a 135 fJ/cycle clock link at 0.7 V supply voltage. A dual-coil transmission scheme reduces the number of stacked transistors in a transmitter, enabling low-voltage and hence low-power operation. A test chip is fabricated in 65 nm CMOS whose nominal supply voltage is 1.2 V. A data rate of 1.1 Gb/s and a clock rate of 3.3 GHz, both with an error rate < 10 -12, are achieved at 0.55 V and 0.7 V supply voltage, respectively.

Original languageEnglish
Article number5720524
Pages (from-to)965-973
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Volume46
Issue number4
DOIs
Publication statusPublished - 2011 Apr

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Clocks
Electric potential
Transmitters
Transistors

Keywords

  • chip stacking
  • Inductive coupling
  • low power
  • three dimensional

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

A 0.55 V 10 fJ/bit inductive-coupling data link and 0.7 V 135 fJ/cycle clock link with dual-coil transmission scheme. / Miura, Noriyuki; Shidei, Tsunaaki; Yuan, Yuxiang; Kawai, Shusuke; Takatsu, Keita; Kiyota, Yuji; Asano, Yuichi; Kuroda, Tadahiro.

In: IEEE Journal of Solid-State Circuits, Vol. 46, No. 4, 5720524, 04.2011, p. 965-973.

Research output: Contribution to journalArticle

Miura, Noriyuki ; Shidei, Tsunaaki ; Yuan, Yuxiang ; Kawai, Shusuke ; Takatsu, Keita ; Kiyota, Yuji ; Asano, Yuichi ; Kuroda, Tadahiro. / A 0.55 V 10 fJ/bit inductive-coupling data link and 0.7 V 135 fJ/cycle clock link with dual-coil transmission scheme. In: IEEE Journal of Solid-State Circuits. 2011 ; Vol. 46, No. 4. pp. 965-973.
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