Abstract
This paper presents an ultra-low-voltage and low-power all-digital (AD) PLL. The AD-PLL consists of time-to-digital converter (TDC) combined 8-phase digitally controlled ring oscillator. The proposed AD-PLL eliminates a delay-line based TDC and suited for ultra-low-voltage and low-power operation in wide frequency range. The AD-PLL designed and fabricated in 40nm-CMOS technology operates with power consumption of 45.5μ\ν at 0.5V power supply and 100MHz output frequency. The AD-PLL has power scalability from 10MHz to 100MHz with normalized power consumption lower than 0.47μW/μηz. The core area is 0.037mm2.
Original language | English |
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Pages | 33-36 |
Number of pages | 4 |
DOIs | |
Publication status | Published - 2012 Dec 1 |
Event | 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 - Kobe, Japan Duration: 2012 Nov 12 → 2012 Nov 14 |
Other
Other | 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 |
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Country | Japan |
City | Kobe |
Period | 12/11/12 → 12/11/14 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering