A 0.5V 10MHz-to-100MHz 0.47μz power scalable AD-PLL in 40nm CMOS

Yasuyuki Hiraku, Isamu Hayashi, Hayun Chung, Tadahiro Kuroda, Hiroki Ishikuro

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

This paper presents an ultra-low-voltage and low-power all-digital (AD) PLL. The AD-PLL consists of time-to-digital converter (TDC) combined 8-phase digitally controlled ring oscillator. The proposed AD-PLL eliminates a delay-line based TDC and suited for ultra-low-voltage and low-power operation in wide frequency range. The AD-PLL designed and fabricated in 40nm-CMOS technology operates with power consumption of 45.5μ\ν at 0.5V power supply and 100MHz output frequency. The AD-PLL has power scalability from 10MHz to 100MHz with normalized power consumption lower than 0.47μW/μηz. The core area is 0.037mm2.

Original languageEnglish
Title of host publicationProceedings - 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC
Pages33-36
Number of pages4
DOIs
Publication statusPublished - 2012
Event2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 - Kobe, Japan
Duration: 2012 Nov 122012 Nov 14

Other

Other2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012
CountryJapan
CityKobe
Period12/11/1212/11/14

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Hiraku, Y., Hayashi, I., Chung, H., Kuroda, T., & Ishikuro, H. (2012). A 0.5V 10MHz-to-100MHz 0.47μz power scalable AD-PLL in 40nm CMOS. In Proceedings - 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC (pp. 33-36). [6522616] https://doi.org/10.1109/IPEC.2012.6522616