A 0.5V 10MHz-to-100MHz 0.47μz power scalable AD-PLL in 40nm CMOS

Yasuyuki Hiraku, Isamu Hayashi, Hayun Chung, Tadahiro Kuroda, Hiroki Ishikuro

    Research output: Contribution to conferencePaperpeer-review

    9 Citations (Scopus)

    Abstract

    This paper presents an ultra-low-voltage and low-power all-digital (AD) PLL. The AD-PLL consists of time-to-digital converter (TDC) combined 8-phase digitally controlled ring oscillator. The proposed AD-PLL eliminates a delay-line based TDC and suited for ultra-low-voltage and low-power operation in wide frequency range. The AD-PLL designed and fabricated in 40nm-CMOS technology operates with power consumption of 45.5μ\ν at 0.5V power supply and 100MHz output frequency. The AD-PLL has power scalability from 10MHz to 100MHz with normalized power consumption lower than 0.47μW/μηz. The core area is 0.037mm2.

    Original languageEnglish
    Pages33-36
    Number of pages4
    DOIs
    Publication statusPublished - 2012 Dec 1
    Event2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 - Kobe, Japan
    Duration: 2012 Nov 122012 Nov 14

    Other

    Other2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012
    CountryJapan
    CityKobe
    Period12/11/1212/11/14

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

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