A 0.5V 1.1MS/sec 6.3fJ/conversion-step SAR-ADC with tri-level comparator in 40nm CMOS

Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro

Research output: Chapter in Book/Report/Conference proceedingConference contribution

37 Citations (Scopus)

Abstract

This paper presents an extremely low-voltage operation and power efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). Tri-level comparator is proposed to relax the speed requirement of the comparator and decrease the resolution of internal Digital-to-Analog Converter (DAC) by 1-bit. The internal DAC employs unit capacitance of 0.5fF and ADC operates at nearly thermal noise limitation. To deal with the problem of capacitor mismatch, reconfigurable capacitor array and calibration procedure were developed. The prototype ADC fabricated using 40nm CMOS process achieves 46.8dB SNDR with 1.1MS/sec at 0.5V power supply. The FoM is 6.3-fJ/conversion step.

Original languageEnglish
Title of host publicationIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Pages262-263
Number of pages2
Publication statusPublished - 2011
Event2011 Symposium on VLSI Circuits, VLSIC 2011 - Kyoto, Japan
Duration: 2011 Jun 152011 Jun 17

Other

Other2011 Symposium on VLSI Circuits, VLSIC 2011
CountryJapan
CityKyoto
Period11/6/1511/6/17

Fingerprint

Digital to analog conversion
Capacitors
Thermal noise
Capacitance
Calibration
Electric potential

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Shikata, A., Sekimoto, R., Kuroda, T., & Ishikuro, H. (2011). A 0.5V 1.1MS/sec 6.3fJ/conversion-step SAR-ADC with tri-level comparator in 40nm CMOS. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers (pp. 262-263). [5986444]

A 0.5V 1.1MS/sec 6.3fJ/conversion-step SAR-ADC with tri-level comparator in 40nm CMOS. / Shikata, Akira; Sekimoto, Ryota; Kuroda, Tadahiro; Ishikuro, Hiroki.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2011. p. 262-263 5986444.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Shikata, A, Sekimoto, R, Kuroda, T & Ishikuro, H 2011, A 0.5V 1.1MS/sec 6.3fJ/conversion-step SAR-ADC with tri-level comparator in 40nm CMOS. in IEEE Symposium on VLSI Circuits, Digest of Technical Papers., 5986444, pp. 262-263, 2011 Symposium on VLSI Circuits, VLSIC 2011, Kyoto, Japan, 11/6/15.
Shikata A, Sekimoto R, Kuroda T, Ishikuro H. A 0.5V 1.1MS/sec 6.3fJ/conversion-step SAR-ADC with tri-level comparator in 40nm CMOS. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2011. p. 262-263. 5986444
Shikata, Akira ; Sekimoto, Ryota ; Kuroda, Tadahiro ; Ishikuro, Hiroki. / A 0.5V 1.1MS/sec 6.3fJ/conversion-step SAR-ADC with tri-level comparator in 40nm CMOS. IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2011. pp. 262-263
@inproceedings{ac0735d3516148eeb349185999bc7830,
title = "A 0.5V 1.1MS/sec 6.3fJ/conversion-step SAR-ADC with tri-level comparator in 40nm CMOS",
abstract = "This paper presents an extremely low-voltage operation and power efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). Tri-level comparator is proposed to relax the speed requirement of the comparator and decrease the resolution of internal Digital-to-Analog Converter (DAC) by 1-bit. The internal DAC employs unit capacitance of 0.5fF and ADC operates at nearly thermal noise limitation. To deal with the problem of capacitor mismatch, reconfigurable capacitor array and calibration procedure were developed. The prototype ADC fabricated using 40nm CMOS process achieves 46.8dB SNDR with 1.1MS/sec at 0.5V power supply. The FoM is 6.3-fJ/conversion step.",
author = "Akira Shikata and Ryota Sekimoto and Tadahiro Kuroda and Hiroki Ishikuro",
year = "2011",
language = "English",
isbn = "9784863481657",
pages = "262--263",
booktitle = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

}

TY - GEN

T1 - A 0.5V 1.1MS/sec 6.3fJ/conversion-step SAR-ADC with tri-level comparator in 40nm CMOS

AU - Shikata, Akira

AU - Sekimoto, Ryota

AU - Kuroda, Tadahiro

AU - Ishikuro, Hiroki

PY - 2011

Y1 - 2011

N2 - This paper presents an extremely low-voltage operation and power efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). Tri-level comparator is proposed to relax the speed requirement of the comparator and decrease the resolution of internal Digital-to-Analog Converter (DAC) by 1-bit. The internal DAC employs unit capacitance of 0.5fF and ADC operates at nearly thermal noise limitation. To deal with the problem of capacitor mismatch, reconfigurable capacitor array and calibration procedure were developed. The prototype ADC fabricated using 40nm CMOS process achieves 46.8dB SNDR with 1.1MS/sec at 0.5V power supply. The FoM is 6.3-fJ/conversion step.

AB - This paper presents an extremely low-voltage operation and power efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). Tri-level comparator is proposed to relax the speed requirement of the comparator and decrease the resolution of internal Digital-to-Analog Converter (DAC) by 1-bit. The internal DAC employs unit capacitance of 0.5fF and ADC operates at nearly thermal noise limitation. To deal with the problem of capacitor mismatch, reconfigurable capacitor array and calibration procedure were developed. The prototype ADC fabricated using 40nm CMOS process achieves 46.8dB SNDR with 1.1MS/sec at 0.5V power supply. The FoM is 6.3-fJ/conversion step.

UR - http://www.scopus.com/inward/record.url?scp=80052678511&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=80052678511&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:80052678511

SN - 9784863481657

SP - 262

EP - 263

BT - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

ER -