### Abstract

This paper presents an extremely low-voltage operation and power efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). Tri-level comparator is proposed to relax the speed requirement of the comparator and decrease the resolution of internal Digital-to-Analog Converter (DAC) by 1-bit. The internal DAC employs unit capacitance of 0.5fF and ADC operates at nearly thermal noise limitation. To deal with the problem of capacitor mismatch, reconfigurable capacitor array and calibration procedure were developed. The prototype ADC fabricated using 40nm CMOS process achieves 46.8dB SNDR with 1.1MS/sec at 0.5V power supply. The FoM is 6.3-fJ/conversion step.

Original language | English |
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Title of host publication | 2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers |

Pages | 262-263 |

Number of pages | 2 |

Publication status | Published - 2011 Sep 16 |

Event | 2011 Symposium on VLSI Circuits, VLSIC 2011 - Kyoto, Japan Duration: 2011 Jun 15 → 2011 Jun 17 |

### Publication series

Name | IEEE Symposium on VLSI Circuits, Digest of Technical Papers |
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### Other

Other | 2011 Symposium on VLSI Circuits, VLSIC 2011 |
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Country | Japan |

City | Kyoto |

Period | 11/6/15 → 11/6/17 |

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### ASJC Scopus subject areas

- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering

### Cite this

*2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers*(pp. 262-263). [5986444] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).