A 0.5V 1.1MS/sec 6.3fJ/conversion-step SAR-ADC with tri-level comparator in 40nm CMOS

Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    37 Citations (Scopus)

    Abstract

    This paper presents an extremely low-voltage operation and power efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). Tri-level comparator is proposed to relax the speed requirement of the comparator and decrease the resolution of internal Digital-to-Analog Converter (DAC) by 1-bit. The internal DAC employs unit capacitance of 0.5fF and ADC operates at nearly thermal noise limitation. To deal with the problem of capacitor mismatch, reconfigurable capacitor array and calibration procedure were developed. The prototype ADC fabricated using 40nm CMOS process achieves 46.8dB SNDR with 1.1MS/sec at 0.5V power supply. The FoM is 6.3-fJ/conversion step.

    Original languageEnglish
    Title of host publication2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers
    Pages262-263
    Number of pages2
    Publication statusPublished - 2011 Sep 16
    Event2011 Symposium on VLSI Circuits, VLSIC 2011 - Kyoto, Japan
    Duration: 2011 Jun 152011 Jun 17

    Publication series

    NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

    Other

    Other2011 Symposium on VLSI Circuits, VLSIC 2011
    CountryJapan
    CityKyoto
    Period11/6/1511/6/17

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering

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  • Cite this

    Shikata, A., Sekimoto, R., Kuroda, T., & Ishikuro, H. (2011). A 0.5V 1.1MS/sec 6.3fJ/conversion-step SAR-ADC with tri-level comparator in 40nm CMOS. In 2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers (pp. 262-263). [5986444] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).