A 0.5V 65nm-CMOS single phase clocked bootstrapped switch with rise time accelerator

Akira Shikata, Ryota Sekimoto, Hiroki Ishikuro

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

This paper presents a twice the supply voltage bootstrapped switch with the proposed rise time accelerator that has high linearity and fast rising with single phase clock input at low voltage. The proposed rise time accelerator improves rising time and ensures circuit operation at extremely low supply voltage without any complex timing generation circuit. The prototype switch is designed in 65nm CMOS process and the simulation results show that the power consumption of quasi differential bootstrapped switch is less than 11nW/MHz at a supply voltage of 0.5V with 10MS/sec. The third order harmonic distortion (HD3) is 104dB with sampling capacitor of 1.28pF.

Original languageEnglish
Title of host publicationIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
Pages1015-1018
Number of pages4
DOIs
Publication statusPublished - 2010
Event2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 - Kuala Lumpur, Malaysia
Duration: 2010 Dec 62010 Dec 9

Other

Other2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
CountryMalaysia
CityKuala Lumpur
Period10/12/610/12/9

Fingerprint

Particle accelerators
Switches
Electric potential
Networks (circuits)
Harmonic distortion
Clocks
Electric power utilization
Capacitors
Sampling

Keywords

  • Bootstrapped Switch
  • Energy harvesting
  • Low voltage
  • Sample and Hold
  • Sensor network
  • Series bootstrapping

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Shikata, A., Sekimoto, R., & Ishikuro, H. (2010). A 0.5V 65nm-CMOS single phase clocked bootstrapped switch with rise time accelerator. In IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS (pp. 1015-1018). [5774976] https://doi.org/10.1109/APCCAS.2010.5774976

A 0.5V 65nm-CMOS single phase clocked bootstrapped switch with rise time accelerator. / Shikata, Akira; Sekimoto, Ryota; Ishikuro, Hiroki.

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. 2010. p. 1015-1018 5774976.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Shikata, A, Sekimoto, R & Ishikuro, H 2010, A 0.5V 65nm-CMOS single phase clocked bootstrapped switch with rise time accelerator. in IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS., 5774976, pp. 1015-1018, 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010, Kuala Lumpur, Malaysia, 10/12/6. https://doi.org/10.1109/APCCAS.2010.5774976
Shikata A, Sekimoto R, Ishikuro H. A 0.5V 65nm-CMOS single phase clocked bootstrapped switch with rise time accelerator. In IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. 2010. p. 1015-1018. 5774976 https://doi.org/10.1109/APCCAS.2010.5774976
Shikata, Akira ; Sekimoto, Ryota ; Ishikuro, Hiroki. / A 0.5V 65nm-CMOS single phase clocked bootstrapped switch with rise time accelerator. IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. 2010. pp. 1015-1018
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