A 0.79-mm2 29-mW real-time face detection core

Yuichi Hori; Tadahiro Kuroda

doi:10.1109/JSSC.2007.891675

A 0.79-mm² 29-mW real-time face detection core

Yuichi Hori, Tadahiro Kuroda

Research output: Contribution to journal › Article › peer-review

21 Citations (Scopus)

Abstract

A 0.79-mm² 29-mW real-time face detection core is fabricated in a 0.13-μm CMOS technology. It consists of 75-kgate logic, 58-kbit SRAM, and an ARM AMBA bus interface. Comprehensive optimization in both algorithm and hardware design improves performance and reduces area and power dissipation. Two kinds of templates with facial features are proposed to achieve high speed and yet accurate face detection. A Steady State Genetic Algorithm is employed for high-speed hardware implementation of template matching. To reduce area and power dissipation, frame memory is optimized at minimum and the detection engine is shared for two kinds of template matching. The core can detect eight faces in each frame of moving pictures at 30 frames/second. Face detection accuracy is 92%.

Original language	English
Pages (from-to)	790-797
Number of pages	8
Journal	IEEE Journal of Solid-State Circuits
Volume	42
Issue number	4
DOIs	https://doi.org/10.1109/JSSC.2007.891675
Publication status	Published - 2007 Apr
Externally published	Yes

Keywords

CMOS
Face recognition
Genetic algorithms
Low power

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/JSSC.2007.891675

Cite this

@article{b8b8420becf345ed8afd8e19144e06b6,

title = "A 0.79-mm2 29-mW real-time face detection core",

abstract = "A 0.79-mm2 29-mW real-time face detection core is fabricated in a 0.13-μm CMOS technology. It consists of 75-kgate logic, 58-kbit SRAM, and an ARM AMBA bus interface. Comprehensive optimization in both algorithm and hardware design improves performance and reduces area and power dissipation. Two kinds of templates with facial features are proposed to achieve high speed and yet accurate face detection. A Steady State Genetic Algorithm is employed for high-speed hardware implementation of template matching. To reduce area and power dissipation, frame memory is optimized at minimum and the detection engine is shared for two kinds of template matching. The core can detect eight faces in each frame of moving pictures at 30 frames/second. Face detection accuracy is 92%.",

keywords = "CMOS, Face recognition, Genetic algorithms, Low power",

author = "Yuichi Hori and Tadahiro Kuroda",

note = "Funding Information: Manuscript received August 25, 2006; revised December 4, 2006. This work was supported by a grant from NuCORE Technology Inc. The authors are with the Department of Electronics and Electrical Engineering, Keio University, Yokohama, Kanagawa 223-8522, Japan (e-mail: hori@kuro.elec.keio.ac.jp). Digital Object Identifier 10.1109/JSSC.2007.891675",

year = "2007",

month = apr,

doi = "10.1109/JSSC.2007.891675",

language = "English",

volume = "42",

pages = "790--797",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "4",

}

TY - JOUR

T1 - A 0.79-mm2 29-mW real-time face detection core

AU - Hori, Yuichi

AU - Kuroda, Tadahiro

N1 - Funding Information: Manuscript received August 25, 2006; revised December 4, 2006. This work was supported by a grant from NuCORE Technology Inc. The authors are with the Department of Electronics and Electrical Engineering, Keio University, Yokohama, Kanagawa 223-8522, Japan (e-mail: hori@kuro.elec.keio.ac.jp). Digital Object Identifier 10.1109/JSSC.2007.891675

PY - 2007/4

Y1 - 2007/4

N2 - A 0.79-mm2 29-mW real-time face detection core is fabricated in a 0.13-μm CMOS technology. It consists of 75-kgate logic, 58-kbit SRAM, and an ARM AMBA bus interface. Comprehensive optimization in both algorithm and hardware design improves performance and reduces area and power dissipation. Two kinds of templates with facial features are proposed to achieve high speed and yet accurate face detection. A Steady State Genetic Algorithm is employed for high-speed hardware implementation of template matching. To reduce area and power dissipation, frame memory is optimized at minimum and the detection engine is shared for two kinds of template matching. The core can detect eight faces in each frame of moving pictures at 30 frames/second. Face detection accuracy is 92%.

AB - A 0.79-mm2 29-mW real-time face detection core is fabricated in a 0.13-μm CMOS technology. It consists of 75-kgate logic, 58-kbit SRAM, and an ARM AMBA bus interface. Comprehensive optimization in both algorithm and hardware design improves performance and reduces area and power dissipation. Two kinds of templates with facial features are proposed to achieve high speed and yet accurate face detection. A Steady State Genetic Algorithm is employed for high-speed hardware implementation of template matching. To reduce area and power dissipation, frame memory is optimized at minimum and the detection engine is shared for two kinds of template matching. The core can detect eight faces in each frame of moving pictures at 30 frames/second. Face detection accuracy is 92%.

KW - CMOS

KW - Face recognition

KW - Genetic algorithms

KW - Low power

UR - http://www.scopus.com/inward/record.url?scp=33947705230&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33947705230&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2007.891675

DO - 10.1109/JSSC.2007.891675

M3 - Article

AN - SCOPUS:33947705230

SN - 0018-9200

VL - 42

SP - 790

EP - 797

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 4

ER -