TY - GEN
T1 - A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique
AU - Yoshioka, Kentaro
AU - Sugimoto, Tomohiko
AU - Waki, Naoya
AU - Kim, Sinnyoung
AU - Kurose, Daisuke
AU - Ishii, Hirotomo
AU - Furuta, Masanori
AU - Sai, Akihide
AU - Itakura, Tetsuro
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/3/2
Y1 - 2017/3/2
N2 - Wireless standards, e.g. 802.11ac Wave 2 and 802.11ax draft, aim to boost user throughput to cope with growing data traffic. High-speed (fs>100MS/s) and high-resolution (ENOB>9.5b) ADCs are essential for leading-edge wireless SoCs, given the bandwidth and PAPR specifications. Also, low power dissipation (FoM<20fJ/conv) is crucial for mobile applications. A number of pipelined-SAR ADCs have been presented which satisfy these design targets [1-3]. However, in deep submicron CMOS, design of a high DC-gain opamp for the MDAC is a serious obstacle due to reduced intrinsic transistor gain and sub-1V supply voltage. Hence, all designs utilize digital calibration to counter gain error and tolerate the use of a low-gain amplifier. Calibration times of at least several tens of ms are required, resulting in lengthy start-up times and reduced SoC power efficiency. Moreover, such calibration cannot track sudden supply voltage variations and suppressing such fluctuations with bypass capacitors significantly impacts chip cost [1-2]. Furthermore, amplifier non-linearity remains unsolved; with lower supply voltages, the limited amplifier swing tightens SAR noise requirements.
AB - Wireless standards, e.g. 802.11ac Wave 2 and 802.11ax draft, aim to boost user throughput to cope with growing data traffic. High-speed (fs>100MS/s) and high-resolution (ENOB>9.5b) ADCs are essential for leading-edge wireless SoCs, given the bandwidth and PAPR specifications. Also, low power dissipation (FoM<20fJ/conv) is crucial for mobile applications. A number of pipelined-SAR ADCs have been presented which satisfy these design targets [1-3]. However, in deep submicron CMOS, design of a high DC-gain opamp for the MDAC is a serious obstacle due to reduced intrinsic transistor gain and sub-1V supply voltage. Hence, all designs utilize digital calibration to counter gain error and tolerate the use of a low-gain amplifier. Calibration times of at least several tens of ms are required, resulting in lengthy start-up times and reduced SoC power efficiency. Moreover, such calibration cannot track sudden supply voltage variations and suppressing such fluctuations with bypass capacitors significantly impacts chip cost [1-2]. Furthermore, amplifier non-linearity remains unsolved; with lower supply voltages, the limited amplifier swing tightens SAR noise requirements.
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U2 - 10.1109/ISSCC.2017.7870469
DO - 10.1109/ISSCC.2017.7870469
M3 - Conference contribution
AN - SCOPUS:85016312126
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 478
EP - 479
BT - 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017
A2 - Fujino, Laura C.
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 64th IEEE International Solid-State Circuits Conference, ISSCC 2017
Y2 - 5 February 2017 through 9 February 2017
ER -