A 0.7V 20fJ/bit inductive-coupling data link with dual-coil transmission scheme

Noriyuki Miura; Tsunaaki Shidei; Yuan Yuxiang; Shusuke Kawai; Keita Takatsu; Yuji Kiyota; Yuichi Asano; Tadahiro Kuroda

doi:10.1109/VLSIC.2010.5560299

A 0.7V 20fJ/bit inductive-coupling data link with dual-coil transmission scheme

Noriyuki Miura, Tsunaaki Shidei, Yuan Yuxiang, Shusuke Kawai, Keita Takatsu, Yuji Kiyota, Yuichi Asano, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Citations (Scopus)

Abstract

This paper presents a 20fJ/bit inductive-coupling data link and a 135fJ/cycle clock link operating at a 0.7V supply voltage. A dual-coil transmission scheme reduces the number of stacked transistors in a transmitter, enabling low-voltage and hence low-power operation. A test chip is fabricated in 65nm CMOS whose nominal supply voltage is 1.2V. A data rate of 1.1Gb/s and a clock rate of 3.3GHz, both with an error rate <10^-12, are achieved at the 0.7V supply voltage.

Original language	English
Title of host publication	2010 Symposium on VLSI Circuits, VLSIC 2010
Pages	201-202
Number of pages	2
DOIs	https://doi.org/10.1109/VLSIC.2010.5560299
Publication status	Published - 2010 Oct 22
Event	2010 24th Symposium on VLSI Circuits, VLSIC 2010 - Honolulu, HI, United States Duration: 2010 Jun 16 → 2010 Jun 18

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	2010 24th Symposium on VLSI Circuits, VLSIC 2010
Country/Territory	United States
City	Honolulu, HI
Period	10/6/16 → 10/6/18

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/VLSIC.2010.5560299

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Miura, N, Shidei, T, Yuxiang, Y, Kawai, S, Takatsu, K, Kiyota, Y, Asano, Y & Kuroda, T 2010, A 0.7V 20fJ/bit inductive-coupling data link with dual-coil transmission scheme. in 2010 Symposium on VLSI Circuits, VLSIC 2010., 5560299, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 201-202, 2010 24th Symposium on VLSI Circuits, VLSIC 2010, Honolulu, HI, United States, 10/6/16. https://doi.org/10.1109/VLSIC.2010.5560299

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abstract = "This paper presents a 20fJ/bit inductive-coupling data link and a 135fJ/cycle clock link operating at a 0.7V supply voltage. A dual-coil transmission scheme reduces the number of stacked transistors in a transmitter, enabling low-voltage and hence low-power operation. A test chip is fabricated in 65nm CMOS whose nominal supply voltage is 1.2V. A data rate of 1.1Gb/s and a clock rate of 3.3GHz, both with an error rate <10-12, are achieved at the 0.7V supply voltage.",

author = "Noriyuki Miura and Tsunaaki Shidei and Yuan Yuxiang and Shusuke Kawai and Keita Takatsu and Yuji Kiyota and Yuichi Asano and Tadahiro Kuroda",

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AU - Miura, Noriyuki

AU - Shidei, Tsunaaki

AU - Yuxiang, Yuan

AU - Kawai, Shusuke

AU - Takatsu, Keita

AU - Kiyota, Yuji

AU - Asano, Yuichi

AU - Kuroda, Tadahiro

PY - 2010/10/22

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N2 - This paper presents a 20fJ/bit inductive-coupling data link and a 135fJ/cycle clock link operating at a 0.7V supply voltage. A dual-coil transmission scheme reduces the number of stacked transistors in a transmitter, enabling low-voltage and hence low-power operation. A test chip is fabricated in 65nm CMOS whose nominal supply voltage is 1.2V. A data rate of 1.1Gb/s and a clock rate of 3.3GHz, both with an error rate <10-12, are achieved at the 0.7V supply voltage.

AB - This paper presents a 20fJ/bit inductive-coupling data link and a 135fJ/cycle clock link operating at a 0.7V supply voltage. A dual-coil transmission scheme reduces the number of stacked transistors in a transmitter, enabling low-voltage and hence low-power operation. A test chip is fabricated in 65nm CMOS whose nominal supply voltage is 1.2V. A data rate of 1.1Gb/s and a clock rate of 3.3GHz, both with an error rate <10-12, are achieved at the 0.7V supply voltage.

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BT - 2010 Symposium on VLSI Circuits, VLSIC 2010

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A 0.7V 20fJ/bit inductive-coupling data link with dual-coil transmission scheme

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