A 0.7V 20fJ/bit inductive-coupling data link with dual-coil transmission scheme

Noriyuki Miura, Tsunaaki Shidei, Yuan Yuxiang, Shusuke Kawai, Keita Takatsu, Yuji Kiyota, Yuichi Asano, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

This paper presents a 20fJ/bit inductive-coupling data link and a 135fJ/cycle clock link operating at a 0.7V supply voltage. A dual-coil transmission scheme reduces the number of stacked transistors in a transmitter, enabling low-voltage and hence low-power operation. A test chip is fabricated in 65nm CMOS whose nominal supply voltage is 1.2V. A data rate of 1.1Gb/s and a clock rate of 3.3GHz, both with an error rate <10-12, are achieved at the 0.7V supply voltage.

Original languageEnglish
Title of host publication2010 Symposium on VLSI Circuits, VLSIC 2010
Pages201-202
Number of pages2
DOIs
Publication statusPublished - 2010 Oct 22
Event2010 24th Symposium on VLSI Circuits, VLSIC 2010 - Honolulu, HI, United States
Duration: 2010 Jun 162010 Jun 18

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2010 24th Symposium on VLSI Circuits, VLSIC 2010
CountryUnited States
CityHonolulu, HI
Period10/6/1610/6/18

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ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Miura, N., Shidei, T., Yuxiang, Y., Kawai, S., Takatsu, K., Kiyota, Y., Asano, Y., & Kuroda, T. (2010). A 0.7V 20fJ/bit inductive-coupling data link with dual-coil transmission scheme. In 2010 Symposium on VLSI Circuits, VLSIC 2010 (pp. 201-202). [5560299] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). https://doi.org/10.1109/VLSIC.2010.5560299