A 0.9-V, 150-MHz, 10-mW, 4 mm", 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme

Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Tetsu Nagamatsu, Shinichi Yoshioka, Kojiro Suzuki, Fumihiko Sano, Masayuki Norishima, Masayuki Murota, Makoto Kako, Masaaki Kinugawa, Masakazu Kakumu, Takayasu Sakurai

Research output: Contribution to journalArticle

302 Citations (Scopus)

Abstract

A 4 mm2, two-dimensional (2-D) 8 × 8 discrete cosine transform (DCT) core processor for HDTV-resolution video compression/decompression in a 0.3-μm CMOS triple-well, double-metal technology operates at 150 MHz from a 0.9-V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3-V design. Circuit techniques for dynamically varying threshold voltage (VT scheme) are introduced to reduce active power dissipation with negligible overhead in speed, standby power dissipation, and chip area. A way to explore VDD -Vth, design space is also studied.

Original languageEnglish
Pages (from-to)1770-1777
Number of pages8
JournalIEEE Journal of Solid-State Circuits
Volume31
Issue number11
Publication statusPublished - 1996 Nov 1
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Kuroda, T., Fujita, T., Mita, S., Nagamatsu, T., Yoshioka, S., Suzuki, K., Sano, F., Norishima, M., Murota, M., Kako, M., Kinugawa, M., Kakumu, M., & Sakurai, T. (1996). A 0.9-V, 150-MHz, 10-mW, 4 mm", 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme. IEEE Journal of Solid-State Circuits, 31(11), 1770-1777.