A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme

Tadahiro Kuroda; Tetsuya Fujita; Shinji Mita; Tetsu Nagamatsu; Shinichi Yoshioka; Kojiro Suzuki; Fumihiko Sano; Masayuki Norishima; Masayuki Murota; Makoto Kako; Masaaki Kinugawa; Masakazu Kakumu; Takayasu Sakurai

doi:10.1109/9780470545058.sect3

A 0.9-V, 150-MHz, 10-mW, 4 mm², 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme

Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Tetsu Nagamatsu, Shinichi Yoshioka, Kojiro Suzuki, Fumihiko Sano, Masayuki Norishima, Masayuki Murota, Makoto Kako, Masaaki Kinugawa, Masakazu Kakumu, Takayasu Sakurai

Research output: Chapter in Book/Report/Conference proceeding › Chapter

Abstract

A 4 mm², two-dimensional (2-D) 8 × 8 discrete cosine transform (DCT) core processor for HDTV-resolution video compression/decompression in a O.3-μ.m CMOS triple-well, double-metal technology operates at 150 MHz from a 0.9-V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3-V design. Circuit techniques for dynamically varying threshold voltage (VT scheme) are introduced to reduce active power dissipation with negligible overhead in speed, standby power dissipation, and chip area. A way to explore V_DD-V_th design space is also studied.

Original language	English
Title of host publication	Low-Power CMOS Design
Publisher	John Wiley and Sons Inc.
Pages	97-104
Number of pages	8
ISBN (Electronic)	9780470545058
ISBN (Print)	9780780334298
DOIs	https://doi.org/10.1109/9780470545058.sect3
Publication status	Published - 1998 Jan 1
Externally published	Yes

ASJC Scopus subject areas

Engineering(all)
Computer Science(all)
Energy(all)

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10.1109/9780470545058.sect3

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Kuroda, T., Fujita, T., Mita, S., Nagamatsu, T., Yoshioka, S., Suzuki, K., Sano, F., Norishima, M., Murota, M., Kako, M., Kinugawa, M., Kakumu, M., & Sakurai, T. (1998). A 0.9-V, 150-MHz, 10-mW, 4 mm², 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme. In Low-Power CMOS Design (pp. 97-104). John Wiley and Sons Inc.. https://doi.org/10.1109/9780470545058.sect3

Kuroda, T, Fujita, T, Mita, S, Nagamatsu, T, Yoshioka, S, Suzuki, K, Sano, F, Norishima, M, Murota, M, Kako, M, Kinugawa, M, Kakumu, M & Sakurai, T 1998, A 0.9-V, 150-MHz, 10-mW, 4 mm², 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme. in Low-Power CMOS Design. John Wiley and Sons Inc., pp. 97-104. https://doi.org/10.1109/9780470545058.sect3

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abstract = "A 4 mm2, two-dimensional (2-D) 8 × 8 discrete cosine transform (DCT) core processor for HDTV-resolution video compression/decompression in a O.3-μ.m CMOS triple-well, double-metal technology operates at 150 MHz from a 0.9-V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3-V design. Circuit techniques for dynamically varying threshold voltage (VT scheme) are introduced to reduce active power dissipation with negligible overhead in speed, standby power dissipation, and chip area. A way to explore VDD-Vth design space is also studied.",

author = "Tadahiro Kuroda and Tetsuya Fujita and Shinji Mita and Tetsu Nagamatsu and Shinichi Yoshioka and Kojiro Suzuki and Fumihiko Sano and Masayuki Norishima and Masayuki Murota and Makoto Kako and Masaaki Kinugawa and Masakazu Kakumu and Takayasu Sakurai",

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AU - Kuroda, Tadahiro

AU - Fujita, Tetsuya

AU - Mita, Shinji

AU - Nagamatsu, Tetsu

AU - Yoshioka, Shinichi

AU - Suzuki, Kojiro

AU - Sano, Fumihiko

AU - Norishima, Masayuki

AU - Murota, Masayuki

AU - Kako, Makoto

AU - Kinugawa, Masaaki

AU - Kakumu, Masakazu

AU - Sakurai, Takayasu

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N2 - A 4 mm2, two-dimensional (2-D) 8 × 8 discrete cosine transform (DCT) core processor for HDTV-resolution video compression/decompression in a O.3-μ.m CMOS triple-well, double-metal technology operates at 150 MHz from a 0.9-V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3-V design. Circuit techniques for dynamically varying threshold voltage (VT scheme) are introduced to reduce active power dissipation with negligible overhead in speed, standby power dissipation, and chip area. A way to explore VDD-Vth design space is also studied.

AB - A 4 mm2, two-dimensional (2-D) 8 × 8 discrete cosine transform (DCT) core processor for HDTV-resolution video compression/decompression in a O.3-μ.m CMOS triple-well, double-metal technology operates at 150 MHz from a 0.9-V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3-V design. Circuit techniques for dynamically varying threshold voltage (VT scheme) are introduced to reduce active power dissipation with negligible overhead in speed, standby power dissipation, and chip area. A way to explore VDD-Vth design space is also studied.

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A 0.9-V, 150-MHz, 10-mW, 4 mm², 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme

Abstract

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