Abstract
A 4 mm2, two-dimensional (2-D) 8 × 8 discrete cosine transform (DCT) core processor for HDTV-resolution video compression/decompression in a O.3-μ.m CMOS triple-well, double-metal technology operates at 150 MHz from a 0.9-V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3-V design. Circuit techniques for dynamically varying threshold voltage (VT scheme) are introduced to reduce active power dissipation with negligible overhead in speed, standby power dissipation, and chip area. A way to explore VDD-Vth design space is also studied.
Original language | English |
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Title of host publication | Low-Power CMOS Design |
Publisher | John Wiley and Sons Inc. |
Pages | 97-104 |
Number of pages | 8 |
ISBN (Electronic) | 9780470545058 |
ISBN (Print) | 9780780334298 |
DOIs | |
Publication status | Published - 1998 Jan 1 |
Externally published | Yes |
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ASJC Scopus subject areas
- Engineering(all)
- Computer Science(all)
- Energy(all)
Cite this
A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme. / Kuroda, Tadahiro; Fujita, Tetsuya; Mita, Shinji; Nagamatsu, Tetsu; Yoshioka, Shinichi; Suzuki, Kojiro; Sano, Fumihiko; Norishima, Masayuki; Murota, Masayuki; Kako, Makoto; Kinugawa, Masaaki; Kakumu, Masakazu; Sakurai, Takayasu.
Low-Power CMOS Design. John Wiley and Sons Inc., 1998. p. 97-104.Research output: Chapter in Book/Report/Conference proceeding › Chapter
}
TY - CHAP
T1 - A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme
AU - Kuroda, Tadahiro
AU - Fujita, Tetsuya
AU - Mita, Shinji
AU - Nagamatsu, Tetsu
AU - Yoshioka, Shinichi
AU - Suzuki, Kojiro
AU - Sano, Fumihiko
AU - Norishima, Masayuki
AU - Murota, Masayuki
AU - Kako, Makoto
AU - Kinugawa, Masaaki
AU - Kakumu, Masakazu
AU - Sakurai, Takayasu
PY - 1998/1/1
Y1 - 1998/1/1
N2 - A 4 mm2, two-dimensional (2-D) 8 × 8 discrete cosine transform (DCT) core processor for HDTV-resolution video compression/decompression in a O.3-μ.m CMOS triple-well, double-metal technology operates at 150 MHz from a 0.9-V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3-V design. Circuit techniques for dynamically varying threshold voltage (VT scheme) are introduced to reduce active power dissipation with negligible overhead in speed, standby power dissipation, and chip area. A way to explore VDD-Vth design space is also studied.
AB - A 4 mm2, two-dimensional (2-D) 8 × 8 discrete cosine transform (DCT) core processor for HDTV-resolution video compression/decompression in a O.3-μ.m CMOS triple-well, double-metal technology operates at 150 MHz from a 0.9-V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3-V design. Circuit techniques for dynamically varying threshold voltage (VT scheme) are introduced to reduce active power dissipation with negligible overhead in speed, standby power dissipation, and chip area. A way to explore VDD-Vth design space is also studied.
UR - http://www.scopus.com/inward/record.url?scp=85051979484&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85051979484&partnerID=8YFLogxK
U2 - 10.1109/9780470545058.sect3
DO - 10.1109/9780470545058.sect3
M3 - Chapter
AN - SCOPUS:85051979484
SN - 9780780334298
SP - 97
EP - 104
BT - Low-Power CMOS Design
PB - John Wiley and Sons Inc.
ER -