A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme

Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Tetsu Nagamatsu, Shinichi Yoshioka, Kojiro Suzuki, Fumihiko Sano, Masayuki Norishima, Masayuki Murota, Makoto Kako, Masaaki Kinugawa, Masakazu Kakumu, Takayasu Sakurai

Research output: Chapter in Book/Report/Conference proceedingChapter


A 4 mm2, two-dimensional (2-D) 8 × 8 discrete cosine transform (DCT) core processor for HDTV-resolution video compression/decompression in a O.3-μ.m CMOS triple-well, double-metal technology operates at 150 MHz from a 0.9-V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3-V design. Circuit techniques for dynamically varying threshold voltage (VT scheme) are introduced to reduce active power dissipation with negligible overhead in speed, standby power dissipation, and chip area. A way to explore VDD-Vth design space is also studied.

Original languageEnglish
Title of host publicationLow-Power CMOS Design
PublisherJohn Wiley and Sons Inc.
Number of pages8
ISBN (Electronic)9780470545058
ISBN (Print)9780780334298
Publication statusPublished - 1998 Jan 1
Externally publishedYes

ASJC Scopus subject areas

  • Engineering(all)
  • Computer Science(all)
  • Energy(all)


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