A 1 GHz CMOS comparator with dynamic offset control technique

Xiaolei Zhu, Sanroku Tsukamoto, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

A dynamic offset control technique that employs charge compensation by timing control is proposed for comparator design in scaled CMOS technology. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25 x 65 μm2 and consumes 380 μW. Circuits for offset control occupies 21% of the areas and 12% of the power consumption of the whole comparator chip.

Original languageEnglish
Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Pages103-104
Number of pages2
DOIs
Publication statusPublished - 2009
EventAsia and South Pacific Design Automation Conference 2009, ASP-DAC 2009 - Yokohama, Japan
Duration: 2009 Jan 192009 Jan 22

Other

OtherAsia and South Pacific Design Automation Conference 2009, ASP-DAC 2009
CountryJapan
CityYokohama
Period09/1/1909/1/22

Fingerprint

Electric power utilization
Networks (circuits)
Compensation and Redress

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

Cite this

Zhu, X., Tsukamoto, S., & Kuroda, T. (2009). A 1 GHz CMOS comparator with dynamic offset control technique. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 103-104). [4796453] https://doi.org/10.1109/ASPDAC.2009.4796453

A 1 GHz CMOS comparator with dynamic offset control technique. / Zhu, Xiaolei; Tsukamoto, Sanroku; Kuroda, Tadahiro.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2009. p. 103-104 4796453.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Zhu, X, Tsukamoto, S & Kuroda, T 2009, A 1 GHz CMOS comparator with dynamic offset control technique. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC., 4796453, pp. 103-104, Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009, Yokohama, Japan, 09/1/19. https://doi.org/10.1109/ASPDAC.2009.4796453
Zhu X, Tsukamoto S, Kuroda T. A 1 GHz CMOS comparator with dynamic offset control technique. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2009. p. 103-104. 4796453 https://doi.org/10.1109/ASPDAC.2009.4796453
Zhu, Xiaolei ; Tsukamoto, Sanroku ; Kuroda, Tadahiro. / A 1 GHz CMOS comparator with dynamic offset control technique. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2009. pp. 103-104
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