A 1 GHz CMOS comparator with dynamic offset control technique

Xiaolei Zhu; Sanroku Tsukamoto; Tadahiro Kuroda

doi:10.1109/ASPDAC.2009.4796453

A 1 GHz CMOS comparator with dynamic offset control technique

Xiaolei Zhu, Sanroku Tsukamoto, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

A dynamic offset control technique that employs charge compensation by timing control is proposed for comparator design in scaled CMOS technology. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25 x 65 μm² and consumes 380 μW. Circuits for offset control occupies 21% of the areas and 12% of the power consumption of the whole comparator chip.

Original language	English
Title of host publication	Proceedings of the ASP-DAC 2009
Subtitle of host publication	Asia and South Pacific Design Automation Conference 2009
Pages	103-104
Number of pages	2
DOIs	https://doi.org/10.1109/ASPDAC.2009.4796453
Publication status	Published - 2009
Event	Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009 - Yokohama, Japan Duration: 2009 Jan 19 → 2009 Jan 22

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other	Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009
Country/Territory	Japan
City	Yokohama
Period	09/1/19 → 09/1/22

ASJC Scopus subject areas

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Access to Document

10.1109/ASPDAC.2009.4796453

Cite this

A 1 GHz CMOS comparator with dynamic offset control technique. / Zhu, Xiaolei; Tsukamoto, Sanroku; Kuroda, Tadahiro.
Proceedings of the ASP-DAC 2009: Asia and South Pacific Design Automation Conference 2009. 2009. p. 103-104 4796453 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Zhu, X, Tsukamoto, S & Kuroda, T 2009, A 1 GHz CMOS comparator with dynamic offset control technique. in Proceedings of the ASP-DAC 2009: Asia and South Pacific Design Automation Conference 2009., 4796453, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 103-104, Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009, Yokohama, Japan, 09/1/19. https://doi.org/10.1109/ASPDAC.2009.4796453

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abstract = "A dynamic offset control technique that employs charge compensation by timing control is proposed for comparator design in scaled CMOS technology. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25 x 65 μm2 and consumes 380 μW. Circuits for offset control occupies 21% of the areas and 12% of the power consumption of the whole comparator chip.",

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AB - A dynamic offset control technique that employs charge compensation by timing control is proposed for comparator design in scaled CMOS technology. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25 x 65 μm2 and consumes 380 μW. Circuits for offset control occupies 21% of the areas and 12% of the power consumption of the whole comparator chip.

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A 1 GHz CMOS comparator with dynamic offset control technique

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