A 1 GHz CMOS comparator with dynamic offset control technique

Xiaolei Zhu, Sanroku Tsukamoto, Tadahiro Kuroda

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)

    Abstract

    A dynamic offset control technique that employs charge compensation by timing control is proposed for comparator design in scaled CMOS technology. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25 x 65 μm2 and consumes 380 μW. Circuits for offset control occupies 21% of the areas and 12% of the power consumption of the whole comparator chip.

    Original languageEnglish
    Title of host publicationProceedings of the ASP-DAC 2009
    Subtitle of host publicationAsia and South Pacific Design Automation Conference 2009
    Pages103-104
    Number of pages2
    DOIs
    Publication statusPublished - 2009 Apr 20
    EventAsia and South Pacific Design Automation Conference 2009, ASP-DAC 2009 - Yokohama, Japan
    Duration: 2009 Jan 192009 Jan 22

    Publication series

    NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

    Other

    OtherAsia and South Pacific Design Automation Conference 2009, ASP-DAC 2009
    CountryJapan
    CityYokohama
    Period09/1/1909/1/22

    ASJC Scopus subject areas

    • Computer Science Applications
    • Computer Graphics and Computer-Aided Design
    • Electrical and Electronic Engineering

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  • Cite this

    Zhu, X., Tsukamoto, S., & Kuroda, T. (2009). A 1 GHz CMOS comparator with dynamic offset control technique. In Proceedings of the ASP-DAC 2009: Asia and South Pacific Design Automation Conference 2009 (pp. 103-104). [4796453] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2009.4796453