A 1 TB/s 1 pJ/b 6.4 mm 2/TB/s QDR inductive-coupling interface between 65-nm CMOS logic and emulated 100-nm DRAM

Noriyuki Miura, Mitsuko Saito, Tadahiro Kuroda

    Research output: Contribution to journalArticlepeer-review

    20 Citations (Scopus)

    Abstract

    1 TB/s 1 pJ/b 6.4 mm 2/TB/s inductive-coupling interface between 65-nm complementary metal-oxide-semiconductor (CMOS) logic and emulated 100-nm dynamic random access memory (DRAM) is developed. BER <10 -16 operation is examined in 1024-bit parallel links. Compared to the latest wired 40-nm DRAM interface, the bandwidth is increased to 32 ×, and the energy consumption and the layout area are reduced to 1/8 and 1/22, respectively.

    Original languageEnglish
    Article number6199998
    Pages (from-to)249-256
    Number of pages8
    JournalIEEE Journal on Emerging and Selected Topics in Circuits and Systems
    Volume2
    Issue number2
    DOIs
    Publication statusPublished - 2012

    Keywords

    • High-bandwidth interface
    • inductive coupling
    • memory-processor stacking
    • three-dimensional integration

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

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