A 1 Tb/s 3 W inductive-coupling transceiver for 3D-stacked inter-chip clock and data link

Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, Takayasu Sakurai, Tadahiro Kuroda

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    40 Citations (Scopus)

    Abstract

    A 1 Tb/s 3 W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1 GHz and data rate of 1 Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30 μm in a layout area of 1 mm 2. The total layout area including 16 clock transceivers is 2 mm 2 in 0.18 μm CMOS and the chip thickness is reduced to 10 μm. Bi-phase modulation (BPM) is employed for the data link to improve noise immunity, reducing power in the transceiver. Four-phase time division multiple access (TDMA) reduces crosstalk and the bit-error rate (BER) is lower than 10 -13.

    Original languageEnglish
    Pages (from-to)111-121
    Number of pages11
    JournalIEEE Journal of Solid-State Circuits
    Volume42
    Issue number1
    DOIs
    Publication statusPublished - 2007 Jan 1

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    Keywords

    • Inductor
    • SiP
    • Three-dimensional
    • Wireless inter-connect

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Cite this

    Miura, N., Mizoguchi, D., Inoue, M., Niitsu, K., Nakagawa, Y., Tago, M., Fukaishi, M., Sakurai, T., & Kuroda, T. (2007). A 1 Tb/s 3 W inductive-coupling transceiver for 3D-stacked inter-chip clock and data link. IEEE Journal of Solid-State Circuits, 42(1), 111-121. https://doi.org/10.1109/JSSC.2006.886554