A 10-bit 80-MS/s decision-select successive approximation TDC in 65-nm CMOS

Hayun Chung, Hiroki Ishikuro, Tadahiro Kuroda

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    34 Citations (Scopus)

    Abstract

    This paper presents a 10-bit 80-MS/s successive approximation time-to-digital converter (TDC) with a decision-select structure for on-chip timing measurement applications. Time-domain successive approximation is realized utilizing a relative timing difference between input and reference timings. While the successive approximation scheme allows high bit resolutions and low power consumptions, the decision-select structure enables fast bit conversions that lead to high sampling rates. The decision-select structure unrolls the successive approximation iteration loop and removes time-consuming timing estimation and adjustment procedures to minimize bit conversion times. As the successive approximation scheme relies on a binary search, exponential delay lines are adopted to achieve good power and noise performances by reducing the total number of delay stages. The proposed TDC uses only 0.048 delay stages per bit conversion. A test-chip prototype fabricated in a 65-nm CMOS technology consumes 9.6 mW at 80-MS/s and demonstrates 0.23-pJ/conversion-step figure-of merit (FOM) and 0.5-LSB single-shot precision.

    Original languageEnglish
    Article number6151852
    Pages (from-to)1232-1241
    Number of pages10
    JournalIEEE Journal of Solid-State Circuits
    Volume47
    Issue number5
    DOIs
    Publication statusPublished - 2012 May 1

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    Keywords

    • Decision-select
    • digital offset calibration
    • high resolution
    • high sampling rate
    • low power
    • successive approximation
    • time-to-digital converter (TDC)

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

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