A 10Gb/s receiver with equalizer and on-chip ISI monitor in 0.11μm CMOS

Yasumoto Tomita, Masaya Kibune, Junji Ogawa, William W. Walker, Hirotaka Tamura, Tadahiro Kuroda

    Research output: Contribution to conferencePaper

    22 Citations (Scopus)

    Abstract

    This paper presents a 10Gb/s receiver that consists of an equalizer, an inter-symbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The Cherry-Hooper topology was employed to realize an adjustable high-bandwidth equalizer with reduced area and power consumption, without using on-chip inductors. The ISI monitor measures the post-cursor and pre-cursor ISI in the equalizer output. The ISI measurement is achieved using a switched-capacitor correlator. A test chip was fabricated in 0.11 μm CMOS. The areas and power consumptions are 47μm x 85μm and 13.2mW for the equalizer and 145μm x 80μm and 10mW for the ISI monitor.

    Original languageEnglish
    Pages202-205
    Number of pages4
    Publication statusPublished - 2004 Sep 29
    Event2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI - Honolulu, HI, United States
    Duration: 2004 Jun 172004 Jun 19

    Other

    Other2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI
    CountryUnited States
    CityHonolulu, HI
    Period04/6/1704/6/19

    Keywords

    • CDR
    • CMOS
    • Equalizer
    • ISI
    • Receiver

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering

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  • Cite this

    Tomita, Y., Kibune, M., Ogawa, J., Walker, W. W., Tamura, H., & Kuroda, T. (2004). A 10Gb/s receiver with equalizer and on-chip ISI monitor in 0.11μm CMOS. 202-205. Paper presented at 2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI, Honolulu, HI, United States.