A 1.2 Gbps non-contact 3D-stacked inter-chip data communications technology

Daisuke Mizoguchi, Noriyuki Miura, Takayasu Sakurai, Tadahiro Kuroda

    Research output: Contribution to journalArticlepeer-review


    A wireless interface for stacked chips in System-in-a-Package is presented. The interface utilizes inductive coupling between metal inductors. S21 parameters of the inductive coupling are measured between chips stacked in face-up for the first time. Calculations from a theoretical model have good agreement with the measurements. A transceiver circuit for Non-Return-to-Zero signaling is developed to reduce power dissipation. The transceiver is implemented in a test chip fabricated in 0.35 μm CMOS and the chips are stacked in face-up. The chips communicate through the transceiver at 1.2 Gb/s/ch with 46 mW power dissipation at 3.3 V over 300 μm distance. A scaling scenario is derived based on the theoretical model and measurement results. It indicates that, if the communication distance is reduced to 13 μm in 70 nm CMOS, 34 Tbps/mm2 will be obtained.

    Original languageEnglish
    Pages (from-to)320-326
    Number of pages7
    JournalIEICE Transactions on Electronics
    Issue number3
    Publication statusPublished - 2006 Jan 1


    • 3D-stacked chips
    • High bandwidth
    • Inductive coupling
    • Low power
    • Wireless superconnect

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering


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