A 12.5 Gbps CDR with differential to common converting edge detector for the wired and wireless serial link

Kaoru Kohira, Hiroki Ishikuro

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

This paper introduces low-power and small area injectionlocking clock and data recovery circuit (CDR) for the wireline and wireless proximity link. By using signal conversion from differential input to common-mode output, the newly proposed edge detector can eliminate the usually used delay line and XOR-based edge detector, and provided low power operation and a small circuit area. The CDR test chip fabricated in a 65-nm CMOS process consumes 30mW from a 1.2-V supply at 12.5 Gbps. The fabricated CDR achieved a BER lower than 10-12 and the recovered clock had an rms jitter of 0.87 ps. The CDR area is 0.165 mm2.

Original languageEnglish
Pages (from-to)458-465
Number of pages8
JournalIEICE Transactions on Electronics
VolumeE99C
Issue number4
DOIs
Publication statusPublished - 2016 Apr 1

Fingerprint

Clock and data recovery circuits (CDR circuits)
Telecommunication links
Detectors
Electric delay lines
Jitter
Clocks
Networks (circuits)

Keywords

  • CDR
  • Edge detectors
  • High speed
  • Injection locking

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

A 12.5 Gbps CDR with differential to common converting edge detector for the wired and wireless serial link. / Kohira, Kaoru; Ishikuro, Hiroki.

In: IEICE Transactions on Electronics, Vol. E99C, No. 4, 01.04.2016, p. 458-465.

Research output: Contribution to journalArticle

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