A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL

Yuki Urano; Won Joo Yun; Tadahiro Kuroda; Hiroki Ishikuro

doi:10.1109/ISCAS.2013.6572161

A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL

Yuki Urano, Won Joo Yun, Tadahiro Kuroda, Hiroki Ishikuro

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Citations (Scopus)

Abstract

This paper presents an all-digital CDR with TDC combined DLL which can be used for not only NRZ signaling but also pulse-based communication. The TDC combined DLL can realize a small area, low power and fast locking by sharing the delay line of the TDC with the DLL. The proposed CDR can recover the clock by evaluating a waveform of one cycle, and detect edge from a pulse-based signal. Locking time is within 8 clock cycles, and power efficiency is 1.26mW/GHz at 1Gbps and 0.7V power supply. The rms and peak-to-peak jitter at 2.3Gbps and 1.0V are 5.44ps and 37.4ps, respectively. Die area is 0.0297mm².

Original language	English
Title of host publication	2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
Pages	1576-1579
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2013.6572161
Publication status	Published - 2013 Sept 9
Event	2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 - Beijing, China Duration: 2013 May 19 → 2013 May 23

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Other

Other	2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
Country/Territory	China
City	Beijing
Period	13/5/19 → 13/5/23

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2013.6572161

Cite this

A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL. / Urano, Yuki; Yun, Won Joo; Kuroda, Tadahiro et al.
2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013. 2013. p. 1576-1579 6572161 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Urano, Y, Yun, WJ, Kuroda, T & Ishikuro, H 2013, A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL. in 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013., 6572161, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 1576-1579, 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013, Beijing, China, 13/5/19. https://doi.org/10.1109/ISCAS.2013.6572161

@inproceedings{f988872ea182431983ecb9f784a8ab53,

title = "A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL",

abstract = "This paper presents an all-digital CDR with TDC combined DLL which can be used for not only NRZ signaling but also pulse-based communication. The TDC combined DLL can realize a small area, low power and fast locking by sharing the delay line of the TDC with the DLL. The proposed CDR can recover the clock by evaluating a waveform of one cycle, and detect edge from a pulse-based signal. Locking time is within 8 clock cycles, and power efficiency is 1.26mW/GHz at 1Gbps and 0.7V power supply. The rms and peak-to-peak jitter at 2.3Gbps and 1.0V are 5.44ps and 37.4ps, respectively. Die area is 0.0297mm2.",

author = "Yuki Urano and Yun, {Won Joo} and Tadahiro Kuroda and Hiroki Ishikuro",

year = "2013",

month = sep,

day = "9",

doi = "10.1109/ISCAS.2013.6572161",

language = "English",

isbn = "9781467357609",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

pages = "1576--1579",

booktitle = "2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013",

note = "2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 ; Conference date: 19-05-2013 Through 23-05-2013",

}

TY - GEN

T1 - A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL

AU - Urano, Yuki

AU - Yun, Won Joo

AU - Kuroda, Tadahiro

AU - Ishikuro, Hiroki

PY - 2013/9/9

Y1 - 2013/9/9

N2 - This paper presents an all-digital CDR with TDC combined DLL which can be used for not only NRZ signaling but also pulse-based communication. The TDC combined DLL can realize a small area, low power and fast locking by sharing the delay line of the TDC with the DLL. The proposed CDR can recover the clock by evaluating a waveform of one cycle, and detect edge from a pulse-based signal. Locking time is within 8 clock cycles, and power efficiency is 1.26mW/GHz at 1Gbps and 0.7V power supply. The rms and peak-to-peak jitter at 2.3Gbps and 1.0V are 5.44ps and 37.4ps, respectively. Die area is 0.0297mm2.

AB - This paper presents an all-digital CDR with TDC combined DLL which can be used for not only NRZ signaling but also pulse-based communication. The TDC combined DLL can realize a small area, low power and fast locking by sharing the delay line of the TDC with the DLL. The proposed CDR can recover the clock by evaluating a waveform of one cycle, and detect edge from a pulse-based signal. Locking time is within 8 clock cycles, and power efficiency is 1.26mW/GHz at 1Gbps and 0.7V power supply. The rms and peak-to-peak jitter at 2.3Gbps and 1.0V are 5.44ps and 37.4ps, respectively. Die area is 0.0297mm2.

UR - http://www.scopus.com/inward/record.url?scp=84883317499&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84883317499&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2013.6572161

DO - 10.1109/ISCAS.2013.6572161

M3 - Conference contribution

AN - SCOPUS:84883317499

SN - 9781467357609

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

SP - 1576

EP - 1579

BT - 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013

T2 - 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013

Y2 - 19 May 2013 through 23 May 2013

ER -

A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL

Abstract

Publication series

Other

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this