A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL

Yuki Urano, Won Joo Yun, Tadahiro Kuroda, Hiroki Ishikuro

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    7 Citations (Scopus)

    Abstract

    This paper presents an all-digital CDR with TDC combined DLL which can be used for not only NRZ signaling but also pulse-based communication. The TDC combined DLL can realize a small area, low power and fast locking by sharing the delay line of the TDC with the DLL. The proposed CDR can recover the clock by evaluating a waveform of one cycle, and detect edge from a pulse-based signal. Locking time is within 8 clock cycles, and power efficiency is 1.26mW/GHz at 1Gbps and 0.7V power supply. The rms and peak-to-peak jitter at 2.3Gbps and 1.0V are 5.44ps and 37.4ps, respectively. Die area is 0.0297mm2.

    Original languageEnglish
    Title of host publication2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
    Pages1576-1579
    Number of pages4
    DOIs
    Publication statusPublished - 2013 Sep 9
    Event2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 - Beijing, China
    Duration: 2013 May 192013 May 23

    Publication series

    NameProceedings - IEEE International Symposium on Circuits and Systems
    ISSN (Print)0271-4310

    Other

    Other2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
    CountryChina
    CityBeijing
    Period13/5/1913/5/23

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

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