A wireless bus for stacked chips is designed with the interface using inductive coupling with metal spiral inductors. Transceiver circuits for non-return-to-zero signaling are developed. Test chips stacked at a distance of 300μm communicate at data rates of up to 1.2Gb/s/pin. Fabricated in 0.35μm CMOS technology, TX and RX dissipation are 43 and 2.5mW, respectively.
|Journal||Digest of Technical Papers - IEEE International Solid-State Circuits Conference|
|Publication status||Published - 2004 Jun 2|
|Event||Digest of Technical Papers - 2004 IEEE International Solid-State Circuits Conference - San Francisco, CA., United States|
Duration: 2003 Feb 15 → 2003 Feb 19
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering