A 1.2Gb/s/pin wireless superconnect based on Inductive Inter-chip Signaling (IIS)

Daisuke Mizoguchi, Yusmeeraz Binti Yusof, Noriyuki Miura, Takayasu Sakurai, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

81 Citations (Scopus)

Abstract

A wireless bus for stacked chips is designed with the interface using inductive coupling with metal spiral inductors. Transceiver circuits for non-return-to-zero signaling are developed. Test chips stacked at a distance of 300μm communicate at data rates of up to 1.2Gb/s/pin. Fabricated in 0.35μm CMOS technology, TX and RX dissipation are 43 and 2.5mW, respectively.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
EditorsL.C. Fujino, M. Amiri, A. Grabel, D. Jaeger, K.C. Smith
Volume47
Publication statusPublished - 2004
EventDigest of Technical Papers - 2004 IEEE International Solid-State Circuits Conference - San Francisco, CA., United States
Duration: 2003 Feb 152003 Feb 19

Other

OtherDigest of Technical Papers - 2004 IEEE International Solid-State Circuits Conference
CountryUnited States
CitySan Francisco, CA.
Period03/2/1503/2/19

    Fingerprint

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

Mizoguchi, D., Yusof, Y. B., Miura, N., Sakurai, T., & Kuroda, T. (2004). A 1.2Gb/s/pin wireless superconnect based on Inductive Inter-chip Signaling (IIS). In L. C. Fujino, M. Amiri, A. Grabel, D. Jaeger, & K. C. Smith (Eds.), Digest of Technical Papers - IEEE International Solid-State Circuits Conference (Vol. 47)