A 1.2Gb/s/pin wireless superconnect based on inductive inter-chip signaling (IIS)

Daisuke Mizoguchi, Yusmeeraz Binti Yusof, Noriyuki Miura, Takayasu Sakurai, Tadahiro Kuroda

    Research output: Contribution to journalConference articlepeer-review

    4 Citations (Scopus)

    Abstract

    A wireless bus for stacked chips is designed with the interface using inductive coupling with metal spiral inductors. Transceiver circuits for non-return-to-zero signaling are developed. Test chips stacked at a distance of 300μm communicate at data rates of up to 1.2Gb/s/pin. Fabricated in 0.35μm CMOS technology, TX and RX dissipation are 43 and 2.5mW, respectively.

    Original languageEnglish
    Pages (from-to)104-105
    Number of pages2
    JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
    Volume47
    Publication statusPublished - 2003 Dec 1
    EventDigest of Technical Papers - IEEE International Solid-State Circuits Conference: Visuals Supplement - San Francisco, CA., United States
    Duration: 2003 Feb 152003 Feb 19

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering

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