A 1.2Gb/s/pin wireless superconnect based on inductive inter-chip signaling (IIS)

Daisuke Mizoguchi; Yusmeeraz Binti Yusof; Noriyuki Miura; Takayasu Sakurai; Tadahiro Kuroda

A 1.2Gb/s/pin wireless superconnect based on inductive inter-chip signaling (IIS)

Daisuke Mizoguchi, Yusmeeraz Binti Yusof, Noriyuki Miura, Takayasu Sakurai, Tadahiro Kuroda

Research output: Contribution to journal › Conference article › peer-review

Abstract

A wireless bus for stacked chips is designed with the interface using inductive coupling with metal spiral inductors. Transceiver circuits for non-return-to-zero signaling are developed. Test chips stacked at a distance of 300μm communicate at data rates of up to 1.2Gb/s/pin. Fabricated in 0.35μm CMOS technology, TX and RX dissipation are 43 and 2.5mW, respectively.

Original language	English
Pages (from-to)	104-105
Number of pages	2
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	47
Publication status	Published - 2003 Dec 1
Event	Digest of Technical Papers - IEEE International Solid-State Circuits Conference: Visuals Supplement - San Francisco, CA., United States Duration: 2003 Feb 15 → 2003 Feb 19

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

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title = "A 1.2Gb/s/pin wireless superconnect based on inductive inter-chip signaling (IIS)",

abstract = "A wireless bus for stacked chips is designed with the interface using inductive coupling with metal spiral inductors. Transceiver circuits for non-return-to-zero signaling are developed. Test chips stacked at a distance of 300μm communicate at data rates of up to 1.2Gb/s/pin. Fabricated in 0.35μm CMOS technology, TX and RX dissipation are 43 and 2.5mW, respectively.",

author = "Daisuke Mizoguchi and Yusof, {Yusmeeraz Binti} and Noriyuki Miura and Takayasu Sakurai and Tadahiro Kuroda",

year = "2003",

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AU - Miura, Noriyuki

AU - Sakurai, Takayasu

AU - Kuroda, Tadahiro

PY - 2003/12/1

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N2 - A wireless bus for stacked chips is designed with the interface using inductive coupling with metal spiral inductors. Transceiver circuits for non-return-to-zero signaling are developed. Test chips stacked at a distance of 300μm communicate at data rates of up to 1.2Gb/s/pin. Fabricated in 0.35μm CMOS technology, TX and RX dissipation are 43 and 2.5mW, respectively.

AB - A wireless bus for stacked chips is designed with the interface using inductive coupling with metal spiral inductors. Transceiver circuits for non-return-to-zero signaling are developed. Test chips stacked at a distance of 300μm communicate at data rates of up to 1.2Gb/s/pin. Fabricated in 0.35μm CMOS technology, TX and RX dissipation are 43 and 2.5mW, respectively.

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JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

T2 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference: Visuals Supplement

Y2 - 15 February 2003 through 19 February 2003

ER -

A 1.2Gb/s/pin wireless superconnect based on inductive inter-chip signaling (IIS)

Abstract

ASJC Scopus subject areas

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