TY - JOUR
T1 - A 14-GHz AC-coupled clock distribution scheme with phase averaging technique using single LC-VCO and distributed phase interpolators
AU - Niitsu, Kiichi
AU - Kulkarni, Vishal V.
AU - Kang, Shinmo
AU - Ishikuro, Hiroki
AU - Kuroda, Tadahiro
N1 - Funding Information:
Manuscript received December 03, 2009; revised March 27, 2010 and June 28, 2010; accepted August 06, 2010. Date of publication September 30, 2010; date of current version September 14, 2011. This work was supported in part by the Grant-in-Aid for JSPS Fellows, by VLSI Design and Education Center (VDEC), by the University of Tokyo in collaboration with Synopsys, Inc., by Cadence Design Systems, Inc., by Mentor Graphics, Inc., and by Agilent Technologies Japan, Ltd.
PY - 2011/11
Y1 - 2011/11
N2 - In this paper, we report the world's first ac-coupled clock distribution circuit for low-power and high-frequency clock distribution. By employing the proposed ac-coupled LC-based voltage-controlled oscillator (LC-VCO) and phase interpolators, the use of conventional current-mode-logic (CML) buffers with large power requirements can be prevented, and power consumption for clock distribution can be reduced. With the aim of verifying the effectiveness of the proposed circuit, test chips were designed and fabricated in 0.18-μm mixed-signal CMOS technology. The measured results indicated a 14.007 GHz clock distribution to four points whose pitches are 450 μ m, with 6.9 mW of power. The phase noise was measured to be -79.06 dBc/Hz at a 100 kHz offset, - 101.66 dBc/Hz at a 1 MHz offset, and -107.25 dBc/Hz at a 10 MHz offset, with a clock frequency of 12.96 GHz. Furthermore, a phase averaging technique for reducing phase deviation was proposed and theoretically investigated.
AB - In this paper, we report the world's first ac-coupled clock distribution circuit for low-power and high-frequency clock distribution. By employing the proposed ac-coupled LC-based voltage-controlled oscillator (LC-VCO) and phase interpolators, the use of conventional current-mode-logic (CML) buffers with large power requirements can be prevented, and power consumption for clock distribution can be reduced. With the aim of verifying the effectiveness of the proposed circuit, test chips were designed and fabricated in 0.18-μm mixed-signal CMOS technology. The measured results indicated a 14.007 GHz clock distribution to four points whose pitches are 450 μ m, with 6.9 mW of power. The phase noise was measured to be -79.06 dBc/Hz at a 100 kHz offset, - 101.66 dBc/Hz at a 1 MHz offset, and -107.25 dBc/Hz at a 10 MHz offset, with a clock frequency of 12.96 GHz. Furthermore, a phase averaging technique for reducing phase deviation was proposed and theoretically investigated.
KW - CMOS integrated circuits (ICs)
KW - Clock distribution
KW - LC-based voltage-controlled oscillator (LC-VCO)
KW - low-power design
KW - voltage-controlled oscillator (VCO)
KW - wireless communication
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U2 - 10.1109/TVLSI.2010.2072794
DO - 10.1109/TVLSI.2010.2072794
M3 - Article
AN - SCOPUS:80052874584
VL - 19
SP - 2058
EP - 2066
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 11
M1 - 5590276
ER -