A 14-GHz AC-coupled clock distribution scheme with phase averaging technique using single LC-VCO and distributed phase interpolators

Kiichi Niitsu, Vishal V. Kulkarni, Shinmo Kang, Hiroki Ishikuro, Tadahiro Kuroda

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

In this paper, we report the world's first ac-coupled clock distribution circuit for low-power and high-frequency clock distribution. By employing the proposed ac-coupled LC-based voltage-controlled oscillator (LC-VCO) and phase interpolators, the use of conventional current-mode-logic (CML) buffers with large power requirements can be prevented, and power consumption for clock distribution can be reduced. With the aim of verifying the effectiveness of the proposed circuit, test chips were designed and fabricated in 0.18-μm mixed-signal CMOS technology. The measured results indicated a 14.007 GHz clock distribution to four points whose pitches are 450 μ m, with 6.9 mW of power. The phase noise was measured to be -79.06 dBc/Hz at a 100 kHz offset, - 101.66 dBc/Hz at a 1 MHz offset, and -107.25 dBc/Hz at a 10 MHz offset, with a clock frequency of 12.96 GHz. Furthermore, a phase averaging technique for reducing phase deviation was proposed and theoretically investigated.

Original languageEnglish
Article number5590276
Pages (from-to)2058-2066
Number of pages9
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume19
Issue number11
DOIs
Publication statusPublished - 2011 Nov 1

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Keywords

  • CMOS integrated circuits (ICs)
  • Clock distribution
  • LC-based voltage-controlled oscillator (LC-VCO)
  • low-power design
  • voltage-controlled oscillator (VCO)
  • wireless communication

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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