A 1.6 GS/s 3.17 mW 6-b passive pipelined binary-search ADC with memory effect canceller and reference voltage calibration

Koki Tanaka, Ryo Saito, Hiroki Ishikuro

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

A 6-bit high-speed and low-power pipelined binary-search ADC is presented. Over GHz conversion rate is achieved by passive pipeline operation without amplifier. 'Memory effect' caused by charge sharing in the passive pipeline operation is cancelled by charge reset and flatness of frequency response of the converter is improved. Memory effect canceller also makes it easy to calibrate reference voltage to each comparator and to enhance SNDR. The prototype ADC fabricated in 40nm-CMOS achieved 29.21 dB SNDR with 1.6 GS/s at supply voltage of 0.9 V. The ADC achieved a FoM of 84.1 fJ/conv.step.

Original languageEnglish
Title of host publicationEuropean Solid-State Circuits Conference
PublisherIEEE Computer Society
Pages327-330
Number of pages4
Volume2015-October
ISBN (Print)9781467374705
DOIs
Publication statusPublished - 2015 Oct 30
Event41st European Solid-State Circuits Conference, ESSCIRC 2015 - Graz, Austria
Duration: 2015 Sep 142015 Sep 18

Other

Other41st European Solid-State Circuits Conference, ESSCIRC 2015
CountryAustria
CityGraz
Period15/9/1415/9/18

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Keywords

  • binary-search ADC
  • memory effect cenceller
  • passive pipeline operation
  • reference voltage calibration

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Tanaka, K., Saito, R., & Ishikuro, H. (2015). A 1.6 GS/s 3.17 mW 6-b passive pipelined binary-search ADC with memory effect canceller and reference voltage calibration. In European Solid-State Circuits Conference (Vol. 2015-October, pp. 327-330). [7313893] IEEE Computer Society. https://doi.org/10.1109/ESSCIRC.2015.7313893