A 1Tb/s 3W inductive-coupling transceiver chip

Noriyuki Miura, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30μm in a layout area of 1mm 2. The total layout area including 16 clock transceivers is 2mm 2 in 0.18μm CMOS and the chip thickness is reduced to 10μm. Simple yet accurate model of inductive coupling is utilized for transceiver design. Bi-Phase Modulation (BPM) is employed for the data link to improve noise immunity, reducing power in the transceiver. 4-phase Time Division Multiplexing (TDM) reduces crosstalk and channel pitch. The BER is lower than 10 -13 with 150ps timing margin.

Original languageEnglish
Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Pages92-93
Number of pages2
DOIs
Publication statusPublished - 2007
EventASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 - Yokohama, Japan
Duration: 2007 Jan 232007 Jan 27

Other

OtherASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
CountryJapan
CityYokohama
Period07/1/2307/1/27

Fingerprint

Transceivers
Clocks
Time division multiplexing
Phase modulation
Crosstalk

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Miura, N., & Kuroda, T. (2007). A 1Tb/s 3W inductive-coupling transceiver chip. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 92-93). [4196002] https://doi.org/10.1109/ASPDAC.2007.357798

A 1Tb/s 3W inductive-coupling transceiver chip. / Miura, Noriyuki; Kuroda, Tadahiro.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2007. p. 92-93 4196002.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Miura, N & Kuroda, T 2007, A 1Tb/s 3W inductive-coupling transceiver chip. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC., 4196002, pp. 92-93, ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007, Yokohama, Japan, 07/1/23. https://doi.org/10.1109/ASPDAC.2007.357798
Miura N, Kuroda T. A 1Tb/s 3W inductive-coupling transceiver chip. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2007. p. 92-93. 4196002 https://doi.org/10.1109/ASPDAC.2007.357798
Miura, Noriyuki ; Kuroda, Tadahiro. / A 1Tb/s 3W inductive-coupling transceiver chip. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2007. pp. 92-93
@inproceedings{50b5d15e6fe0413fb1c6aea97fe90ef3,
title = "A 1Tb/s 3W inductive-coupling transceiver chip",
abstract = "A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30μm in a layout area of 1mm 2. The total layout area including 16 clock transceivers is 2mm 2 in 0.18μm CMOS and the chip thickness is reduced to 10μm. Simple yet accurate model of inductive coupling is utilized for transceiver design. Bi-Phase Modulation (BPM) is employed for the data link to improve noise immunity, reducing power in the transceiver. 4-phase Time Division Multiplexing (TDM) reduces crosstalk and channel pitch. The BER is lower than 10 -13 with 150ps timing margin.",
author = "Noriyuki Miura and Tadahiro Kuroda",
year = "2007",
doi = "10.1109/ASPDAC.2007.357798",
language = "English",
isbn = "1424406293",
pages = "92--93",
booktitle = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

}

TY - GEN

T1 - A 1Tb/s 3W inductive-coupling transceiver chip

AU - Miura, Noriyuki

AU - Kuroda, Tadahiro

PY - 2007

Y1 - 2007

N2 - A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30μm in a layout area of 1mm 2. The total layout area including 16 clock transceivers is 2mm 2 in 0.18μm CMOS and the chip thickness is reduced to 10μm. Simple yet accurate model of inductive coupling is utilized for transceiver design. Bi-Phase Modulation (BPM) is employed for the data link to improve noise immunity, reducing power in the transceiver. 4-phase Time Division Multiplexing (TDM) reduces crosstalk and channel pitch. The BER is lower than 10 -13 with 150ps timing margin.

AB - A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30μm in a layout area of 1mm 2. The total layout area including 16 clock transceivers is 2mm 2 in 0.18μm CMOS and the chip thickness is reduced to 10μm. Simple yet accurate model of inductive coupling is utilized for transceiver design. Bi-Phase Modulation (BPM) is employed for the data link to improve noise immunity, reducing power in the transceiver. 4-phase Time Division Multiplexing (TDM) reduces crosstalk and channel pitch. The BER is lower than 10 -13 with 150ps timing margin.

UR - http://www.scopus.com/inward/record.url?scp=46649099879&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=46649099879&partnerID=8YFLogxK

U2 - 10.1109/ASPDAC.2007.357798

DO - 10.1109/ASPDAC.2007.357798

M3 - Conference contribution

SN - 1424406293

SN - 9781424406296

SP - 92

EP - 93

BT - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

ER -