A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link

Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, Takayasu Sakurai, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

83 Citations (Scopus)

Abstract

A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30μm. The total layout area is 2mm2 in 0.18μm CMOS and the chip thickness is 10μm. 4-phase TDMA reduces crosstalk and the BER is <10-12. Bi-phase modulation is used to improve noise immunity, reducing power in the transceiver.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Publication statusPublished - 2006
Event2006 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States
Duration: 2006 Feb 62006 Feb 9

Other

Other2006 IEEE International Solid-State Circuits Conference, ISSCC
CountryUnited States
CitySan Francisco, CA
Period06/2/606/2/9

Fingerprint

Transceivers
Clocks
Time division multiple access
Phase modulation
Crosstalk

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

Miura, N., Mizoguchi, D., Inoue, M., Niitsu, K., Nakagawa, Y., Tago, M., ... Kuroda, T. (2006). A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference [1696223]

A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link. / Miura, Noriyuki; Mizoguchi, Daisuke; Inoue, Mari; Niitsu, Kiichi; Nakagawa, Yoshihiro; Tago, Masamoto; Fukaishi, Muneo; Sakurai, Takayasu; Kuroda, Tadahiro.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2006. 1696223.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Miura, N, Mizoguchi, D, Inoue, M, Niitsu, K, Nakagawa, Y, Tago, M, Fukaishi, M, Sakurai, T & Kuroda, T 2006, A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link. in Digest of Technical Papers - IEEE International Solid-State Circuits Conference., 1696223, 2006 IEEE International Solid-State Circuits Conference, ISSCC, San Francisco, CA, United States, 06/2/6.
Miura N, Mizoguchi D, Inoue M, Niitsu K, Nakagawa Y, Tago M et al. A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2006. 1696223
Miura, Noriyuki ; Mizoguchi, Daisuke ; Inoue, Mari ; Niitsu, Kiichi ; Nakagawa, Yoshihiro ; Tago, Masamoto ; Fukaishi, Muneo ; Sakurai, Takayasu ; Kuroda, Tadahiro. / A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link. Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2006.
@inproceedings{43bec5976083432db90bbc72f3bf3d23,
title = "A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link",
abstract = "A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30μm. The total layout area is 2mm2 in 0.18μm CMOS and the chip thickness is 10μm. 4-phase TDMA reduces crosstalk and the BER is <10-12. Bi-phase modulation is used to improve noise immunity, reducing power in the transceiver.",
author = "Noriyuki Miura and Daisuke Mizoguchi and Mari Inoue and Kiichi Niitsu and Yoshihiro Nakagawa and Masamoto Tago and Muneo Fukaishi and Takayasu Sakurai and Tadahiro Kuroda",
year = "2006",
language = "English",
isbn = "1424400791",
booktitle = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

}

TY - GEN

T1 - A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link

AU - Miura, Noriyuki

AU - Mizoguchi, Daisuke

AU - Inoue, Mari

AU - Niitsu, Kiichi

AU - Nakagawa, Yoshihiro

AU - Tago, Masamoto

AU - Fukaishi, Muneo

AU - Sakurai, Takayasu

AU - Kuroda, Tadahiro

PY - 2006

Y1 - 2006

N2 - A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30μm. The total layout area is 2mm2 in 0.18μm CMOS and the chip thickness is 10μm. 4-phase TDMA reduces crosstalk and the BER is <10-12. Bi-phase modulation is used to improve noise immunity, reducing power in the transceiver.

AB - A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30μm. The total layout area is 2mm2 in 0.18μm CMOS and the chip thickness is 10μm. 4-phase TDMA reduces crosstalk and the BER is <10-12. Bi-phase modulation is used to improve noise immunity, reducing power in the transceiver.

UR - http://www.scopus.com/inward/record.url?scp=33846207670&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33846207670&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:33846207670

SN - 1424400791

SN - 9781424400799

BT - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

ER -