A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link

Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, Takayasu Sakurai, Tadahiro Kuroda

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    84 Citations (Scopus)

    Abstract

    A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30μm. The total layout area is 2mm2 in 0.18μm CMOS and the chip thickness is 10μm. 4-phase TDMA reduces crosstalk and the BER is <10-12. Bi-phase modulation is used to improve noise immunity, reducing power in the transceiver.

    Original languageEnglish
    Title of host publication2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
    Pages424+417
    Publication statusPublished - 2006
    Event2006 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States
    Duration: 2006 Feb 62006 Feb 9

    Publication series

    NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
    ISSN (Print)0193-6530

    Other

    Other2006 IEEE International Solid-State Circuits Conference, ISSCC
    Country/TerritoryUnited States
    CitySan Francisco, CA
    Period06/2/606/2/9

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering

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