A 20-GHz injection-locked LC divider with a 25-% locking range

Takayuki Shibasaki, Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa, Tadahiro Kuroda

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    12 Citations (Scopus)

    Abstract

    A 20-GHz injection-locked LC divider is described. A Miller divider topology was employed along with a coupling circuit to maximize the locking range. A test chip designed in a 90-nm CMOS technology operates at 20 GHz with 25-% locking range while consuming 6.4 m W of power.

    Original languageEnglish
    Title of host publication2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
    Pages170-171
    Number of pages2
    Publication statusPublished - 2006 Dec 1
    Event2006 Symposium on VLSI Circuits, VLSIC - Honolulu, HI, United States
    Duration: 2006 Jun 152006 Jun 17

    Publication series

    NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

    Other

    Other2006 Symposium on VLSI Circuits, VLSIC
    CountryUnited States
    CityHonolulu, HI
    Period06/6/1506/6/17

    Keywords

    • CMOS
    • Frequency divider
    • Injection locking
    • Miller divider
    • Quadrature
    • Voltage-controlled oscillator (VCO)

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering

    Fingerprint Dive into the research topics of 'A 20-GHz injection-locked LC divider with a 25-% locking range'. Together they form a unique fingerprint.

    Cite this