A 24 mW 5.7 Gbps dual frequency conversion demodulator for impulse radio with the first sidelobe

Kaoru Kohira, Naoki Kitazawa, Hiroki Ishikuro

    Research output: Contribution to journalArticlepeer-review

    Abstract

    This paper presents a modulation scheme for impulse radio that uses the first sidelobe for transmitting a non-return-to-zero baseband signal and the implementation of a dual frequency conversion demodulator. The proposed modulation technique realizes two times higher frequency efficiency than that realized by binary phase-shift keying modulation and does not require an up-converter in the transmitter. The dual frequency conversion demodulator compensates for the spectrum distortion caused by the frequency response of the circuits and channel. The effect of frequency compensation is analytically studied. The fabricated demodulator test chip of 65 nm CMOS achieves clock and data recovery at 5.7 Gbps with a power consumption of 24 mW.

    Original languageEnglish
    Pages (from-to)1164-1173
    Number of pages10
    JournalIEICE Transactions on Electronics
    VolumeE99C
    Issue number10
    DOIs
    Publication statusPublished - 2016 Oct 1

    Keywords

    • Clock recovery
    • Impulse radio
    • Sidelobe
    • UWB

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering

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