A 24 mW 5.7 Gbps dual frequency conversion demodulator for impulse radio with the first sidelobe

Kaoru Kohira, Naoki Kitazawa, Hiroki Ishikuro

Research output: Contribution to journalArticle

Abstract

This paper presents a modulation scheme for impulse radio that uses the first sidelobe for transmitting a non-return-to-zero baseband signal and the implementation of a dual frequency conversion demodulator. The proposed modulation technique realizes two times higher frequency efficiency than that realized by binary phase-shift keying modulation and does not require an up-converter in the transmitter. The dual frequency conversion demodulator compensates for the spectrum distortion caused by the frequency response of the circuits and channel. The effect of frequency compensation is analytically studied. The fabricated demodulator test chip of 65 nm CMOS achieves clock and data recovery at 5.7 Gbps with a power consumption of 24 mW.

Original languageEnglish
Pages (from-to)1164-1173
Number of pages10
JournalIEICE Transactions on Electronics
VolumeE99C
Issue number10
DOIs
Publication statusPublished - 2016 Oct 1

Fingerprint

Demodulators
Modulation
Binary phase shift keying
Frequency response
Clocks
Transmitters
Electric power utilization
Recovery
Networks (circuits)

Keywords

  • Clock recovery
  • Impulse radio
  • Sidelobe
  • UWB

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

A 24 mW 5.7 Gbps dual frequency conversion demodulator for impulse radio with the first sidelobe. / Kohira, Kaoru; Kitazawa, Naoki; Ishikuro, Hiroki.

In: IEICE Transactions on Electronics, Vol. E99C, No. 10, 01.10.2016, p. 1164-1173.

Research output: Contribution to journalArticle

@article{d2041bbe3c964d25a743b2aee80dc546,
title = "A 24 mW 5.7 Gbps dual frequency conversion demodulator for impulse radio with the first sidelobe",
abstract = "This paper presents a modulation scheme for impulse radio that uses the first sidelobe for transmitting a non-return-to-zero baseband signal and the implementation of a dual frequency conversion demodulator. The proposed modulation technique realizes two times higher frequency efficiency than that realized by binary phase-shift keying modulation and does not require an up-converter in the transmitter. The dual frequency conversion demodulator compensates for the spectrum distortion caused by the frequency response of the circuits and channel. The effect of frequency compensation is analytically studied. The fabricated demodulator test chip of 65 nm CMOS achieves clock and data recovery at 5.7 Gbps with a power consumption of 24 mW.",
keywords = "Clock recovery, Impulse radio, Sidelobe, UWB",
author = "Kaoru Kohira and Naoki Kitazawa and Hiroki Ishikuro",
year = "2016",
month = "10",
day = "1",
doi = "10.1587/transele.E99.C.1164",
language = "English",
volume = "E99C",
pages = "1164--1173",
journal = "IEICE Transactions on Electronics",
issn = "0916-8524",
publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
number = "10",

}

TY - JOUR

T1 - A 24 mW 5.7 Gbps dual frequency conversion demodulator for impulse radio with the first sidelobe

AU - Kohira, Kaoru

AU - Kitazawa, Naoki

AU - Ishikuro, Hiroki

PY - 2016/10/1

Y1 - 2016/10/1

N2 - This paper presents a modulation scheme for impulse radio that uses the first sidelobe for transmitting a non-return-to-zero baseband signal and the implementation of a dual frequency conversion demodulator. The proposed modulation technique realizes two times higher frequency efficiency than that realized by binary phase-shift keying modulation and does not require an up-converter in the transmitter. The dual frequency conversion demodulator compensates for the spectrum distortion caused by the frequency response of the circuits and channel. The effect of frequency compensation is analytically studied. The fabricated demodulator test chip of 65 nm CMOS achieves clock and data recovery at 5.7 Gbps with a power consumption of 24 mW.

AB - This paper presents a modulation scheme for impulse radio that uses the first sidelobe for transmitting a non-return-to-zero baseband signal and the implementation of a dual frequency conversion demodulator. The proposed modulation technique realizes two times higher frequency efficiency than that realized by binary phase-shift keying modulation and does not require an up-converter in the transmitter. The dual frequency conversion demodulator compensates for the spectrum distortion caused by the frequency response of the circuits and channel. The effect of frequency compensation is analytically studied. The fabricated demodulator test chip of 65 nm CMOS achieves clock and data recovery at 5.7 Gbps with a power consumption of 24 mW.

KW - Clock recovery

KW - Impulse radio

KW - Sidelobe

KW - UWB

UR - http://www.scopus.com/inward/record.url?scp=84992154008&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84992154008&partnerID=8YFLogxK

U2 - 10.1587/transele.E99.C.1164

DO - 10.1587/transele.E99.C.1164

M3 - Article

AN - SCOPUS:84992154008

VL - E99C

SP - 1164

EP - 1173

JO - IEICE Transactions on Electronics

JF - IEICE Transactions on Electronics

SN - 0916-8524

IS - 10

ER -