A 24mW 5.5Gbps dual frequency conversion demodulator for impulse-radio with first sidelobe

Kaoru Kohira; Naoki Kitazawa; Hiroki Ishikuro

doi:10.1109/RWS.2016.7444349

A 24mW 5.5Gbps dual frequency conversion demodulator for impulse-radio with first sidelobe

Kaoru Kohira, Naoki Kitazawa, Hiroki Ishikuro

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents a modulation scheme of impulse radio which uses 1st sidelobe of transmitting NRZ baseband signal and implementation of dual frequency conversion demodulator. The proposed modulation technique realizes two times higher frequency efficiency than that of BPSK modulation and does not require up-converter in the transmitter. The dual frequency conversion demodulator compensates the spectrum distortion caused by frequency response of circuits and channel. The fabricated demodulator test chip in 65nm CMOS achieved clock and data recovery at 5.5Gbps with power consumption of 24mW.

Original language	English
Title of host publication	IEEE Radio and Wireless Symposium, RWS
Publisher	IEEE Computer Society
Pages	10-12
Number of pages	3
Volume	2016-March
ISBN (Print)	9781467398053
DOIs	https://doi.org/10.1109/RWS.2016.7444349
Publication status	Published - 2016 Mar 30
Event	IEEE Radio and Wireless Symposium, RWS 2016 - Austin, United States Duration: 2016 Jan 24 → 2016 Jan 27

Other

Other	IEEE Radio and Wireless Symposium, RWS 2016
Country/Territory	United States
City	Austin
Period	16/1/24 → 16/1/27

Keywords

clock recovery
impulse radio
Sidelobe
UWB

ASJC Scopus subject areas

Computer Networks and Communications
Computer Science Applications
Electrical and Electronic Engineering
Communication

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10.1109/RWS.2016.7444349

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@inproceedings{703f785652294e47a91f693828e671ee,

title = "A 24mW 5.5Gbps dual frequency conversion demodulator for impulse-radio with first sidelobe",

abstract = "This paper presents a modulation scheme of impulse radio which uses 1st sidelobe of transmitting NRZ baseband signal and implementation of dual frequency conversion demodulator. The proposed modulation technique realizes two times higher frequency efficiency than that of BPSK modulation and does not require up-converter in the transmitter. The dual frequency conversion demodulator compensates the spectrum distortion caused by frequency response of circuits and channel. The fabricated demodulator test chip in 65nm CMOS achieved clock and data recovery at 5.5Gbps with power consumption of 24mW.",

keywords = "clock recovery, impulse radio, Sidelobe, UWB",

author = "Kaoru Kohira and Naoki Kitazawa and Hiroki Ishikuro",

year = "2016",

month = mar,

day = "30",

doi = "10.1109/RWS.2016.7444349",

language = "English",

isbn = "9781467398053",

volume = "2016-March",

pages = "10--12",

booktitle = "IEEE Radio and Wireless Symposium, RWS",

publisher = "IEEE Computer Society",

note = "IEEE Radio and Wireless Symposium, RWS 2016 ; Conference date: 24-01-2016 Through 27-01-2016",

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TY - GEN

T1 - A 24mW 5.5Gbps dual frequency conversion demodulator for impulse-radio with first sidelobe

AU - Kohira, Kaoru

AU - Kitazawa, Naoki

AU - Ishikuro, Hiroki

PY - 2016/3/30

Y1 - 2016/3/30

N2 - This paper presents a modulation scheme of impulse radio which uses 1st sidelobe of transmitting NRZ baseband signal and implementation of dual frequency conversion demodulator. The proposed modulation technique realizes two times higher frequency efficiency than that of BPSK modulation and does not require up-converter in the transmitter. The dual frequency conversion demodulator compensates the spectrum distortion caused by frequency response of circuits and channel. The fabricated demodulator test chip in 65nm CMOS achieved clock and data recovery at 5.5Gbps with power consumption of 24mW.

AB - This paper presents a modulation scheme of impulse radio which uses 1st sidelobe of transmitting NRZ baseband signal and implementation of dual frequency conversion demodulator. The proposed modulation technique realizes two times higher frequency efficiency than that of BPSK modulation and does not require up-converter in the transmitter. The dual frequency conversion demodulator compensates the spectrum distortion caused by frequency response of circuits and channel. The fabricated demodulator test chip in 65nm CMOS achieved clock and data recovery at 5.5Gbps with power consumption of 24mW.

KW - clock recovery

KW - impulse radio

KW - Sidelobe

KW - UWB

UR - http://www.scopus.com/inward/record.url?scp=84964659848&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84964659848&partnerID=8YFLogxK

U2 - 10.1109/RWS.2016.7444349

DO - 10.1109/RWS.2016.7444349

M3 - Conference contribution

AN - SCOPUS:84964659848

SN - 9781467398053

VL - 2016-March

SP - 10

EP - 12

BT - IEEE Radio and Wireless Symposium, RWS

PB - IEEE Computer Society

T2 - IEEE Radio and Wireless Symposium, RWS 2016

Y2 - 24 January 2016 through 27 January 2016

ER -

A 24mW 5.5Gbps dual frequency conversion demodulator for impulse-radio with first sidelobe

Abstract

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Keywords

ASJC Scopus subject areas

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