A 24mW 5.5Gbps dual frequency conversion demodulator for impulse-radio with first sidelobe

Kaoru Kohira, Naoki Kitazawa, Hiroki Ishikuro

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a modulation scheme of impulse radio which uses 1st sidelobe of transmitting NRZ baseband signal and implementation of dual frequency conversion demodulator. The proposed modulation technique realizes two times higher frequency efficiency than that of BPSK modulation and does not require up-converter in the transmitter. The dual frequency conversion demodulator compensates the spectrum distortion caused by frequency response of circuits and channel. The fabricated demodulator test chip in 65nm CMOS achieved clock and data recovery at 5.5Gbps with power consumption of 24mW.

Original languageEnglish
Title of host publicationIEEE Radio and Wireless Symposium, RWS
PublisherIEEE Computer Society
Pages10-12
Number of pages3
Volume2016-March
ISBN (Print)9781467398053
DOIs
Publication statusPublished - 2016 Mar 30
EventIEEE Radio and Wireless Symposium, RWS 2016 - Austin, United States
Duration: 2016 Jan 242016 Jan 27

Other

OtherIEEE Radio and Wireless Symposium, RWS 2016
CountryUnited States
CityAustin
Period16/1/2416/1/27

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Keywords

  • clock recovery
  • impulse radio
  • Sidelobe
  • UWB

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Computer Science Applications
  • Electrical and Electronic Engineering
  • Communication

Cite this

Kohira, K., Kitazawa, N., & Ishikuro, H. (2016). A 24mW 5.5Gbps dual frequency conversion demodulator for impulse-radio with first sidelobe. In IEEE Radio and Wireless Symposium, RWS (Vol. 2016-March, pp. 10-12). [7444349] IEEE Computer Society. https://doi.org/10.1109/RWS.2016.7444349