A 2.7Gb/s/mm2 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND flash memory stacking

Noriyuki Miura, Yasuhiro Take, Mitsuko Saito, Yoichi Yoshida, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Abstract

This paper presents an inductive-coupling interface for NAND Flash memory stacking whose bandwidth per unit area is 2.7Gb/s/mm2 and energy consumption per chip is 0.9pJ/b/chip. The bandwidth is increased by 10x (in other words, layout area is reduced to 1/10 for the same data rate), and the energy consumption is reduced by half, both compared to the latest research results [1]. A relayed transmission scheme using one coil is proposed to reduce the number of coils in a data link. Coupled resonation is utilized for clock and data recovery (CDR) for the first time in the world, resulting in elimination of a source synchronous clock link. As a result, total number of coils needed to form a channel is reduced from 6 to 1, yielding the significant improvement in data rate, layout area and energy consumption.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Pages490-491
Number of pages2
DOIs
Publication statusPublished - 2011
Event2011 IEEE International Solid-State Circuits Conference, ISSCC 2011 - San Francisco, CA, United States
Duration: 2011 Feb 202011 Feb 24

Other

Other2011 IEEE International Solid-State Circuits Conference, ISSCC 2011
CountryUnited States
CitySan Francisco, CA
Period11/2/2011/2/24

Fingerprint

Flash memory
Clocks
Resonators
Energy utilization
Recovery
Bandwidth

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Miura, N., Take, Y., Saito, M., Yoshida, Y., & Kuroda, T. (2011). A 2.7Gb/s/mm2 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND flash memory stacking. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference (pp. 490-491). [5746410] https://doi.org/10.1109/ISSCC.2011.5746410

A 2.7Gb/s/mm2 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND flash memory stacking. / Miura, Noriyuki; Take, Yasuhiro; Saito, Mitsuko; Yoshida, Yoichi; Kuroda, Tadahiro.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2011. p. 490-491 5746410.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Miura, N, Take, Y, Saito, M, Yoshida, Y & Kuroda, T 2011, A 2.7Gb/s/mm2 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND flash memory stacking. in Digest of Technical Papers - IEEE International Solid-State Circuits Conference., 5746410, pp. 490-491, 2011 IEEE International Solid-State Circuits Conference, ISSCC 2011, San Francisco, CA, United States, 11/2/20. https://doi.org/10.1109/ISSCC.2011.5746410
Miura N, Take Y, Saito M, Yoshida Y, Kuroda T. A 2.7Gb/s/mm2 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND flash memory stacking. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2011. p. 490-491. 5746410 https://doi.org/10.1109/ISSCC.2011.5746410
Miura, Noriyuki ; Take, Yasuhiro ; Saito, Mitsuko ; Yoshida, Yoichi ; Kuroda, Tadahiro. / A 2.7Gb/s/mm2 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND flash memory stacking. Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2011. pp. 490-491
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