A 297mops/0.4mw ultra low power coarse-grained reconfigurable accelerator CMA-SOTB-2

Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

Cool mega array-SOTB-2 (CMA-SOTB-2) is an ultra-low energy coarse grained reconfigurable architecture (CGRA) for advanced sensor networks, the Internet of Things, and wearable computing. It uses a large processing element (PE) array with combinatorial circuits and a micro-controller for data transfer between data memory and the PE array. To improve the energy efficiency of the previous prototype, the CMA-SOTB, the performance of the micro-controller was improved by introducing parallel data memory access with data manipulators and optimization of both instruction sets and micro-architecture. A delay learning mechanism that finds the optimal delay time for the computation in the PE array is also introduced. Standard cell libraries of the 65nm silicon on thin buried oxide (SOTB) process have been optimized for under-milliwatt operation. A real chip evaluation shows that more than 250-MOPS performance was achieved with only a 0.4-mW power budget by independently controlling the body-bias voltage for the micro-controller and the PE array. The energy efficiency is almost double that of the previous prototype, the CMA-SOTB.

Original languageEnglish
Title of host publication2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781467394062
DOIs
Publication statusPublished - 2016 Jan 25
EventInternational Conference on ReConFigurable Computing and FPGAs, ReConFig 2015 - Riviera Maya, Mexico
Duration: 2015 Dec 72015 Dec 9

Other

OtherInternational Conference on ReConFigurable Computing and FPGAs, ReConFig 2015
CountryMexico
CityRiviera Maya
Period15/12/715/12/9

Fingerprint

Particle accelerators
Silicon
Oxides
Processing
Controllers
Energy efficiency
Reconfigurable architectures
Data storage equipment
Combinatorial circuits
Data transfer
Bias voltage
Sensor networks
Manipulators
Time delay

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software

Cite this

Masuyama, K., Fujita, Y., Okuhara, H., & Amano, H. (2016). A 297mops/0.4mw ultra low power coarse-grained reconfigurable accelerator CMA-SOTB-2. In 2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015 [7393280] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ReConFig.2015.7393280

A 297mops/0.4mw ultra low power coarse-grained reconfigurable accelerator CMA-SOTB-2. / Masuyama, Koichiro; Fujita, Yu; Okuhara, Hayate; Amano, Hideharu.

2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015. Institute of Electrical and Electronics Engineers Inc., 2016. 7393280.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Masuyama, K, Fujita, Y, Okuhara, H & Amano, H 2016, A 297mops/0.4mw ultra low power coarse-grained reconfigurable accelerator CMA-SOTB-2. in 2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015., 7393280, Institute of Electrical and Electronics Engineers Inc., International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015, Riviera Maya, Mexico, 15/12/7. https://doi.org/10.1109/ReConFig.2015.7393280
Masuyama K, Fujita Y, Okuhara H, Amano H. A 297mops/0.4mw ultra low power coarse-grained reconfigurable accelerator CMA-SOTB-2. In 2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015. Institute of Electrical and Electronics Engineers Inc. 2016. 7393280 https://doi.org/10.1109/ReConFig.2015.7393280
Masuyama, Koichiro ; Fujita, Yu ; Okuhara, Hayate ; Amano, Hideharu. / A 297mops/0.4mw ultra low power coarse-grained reconfigurable accelerator CMA-SOTB-2. 2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015. Institute of Electrical and Electronics Engineers Inc., 2016.
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