A 2Gb/s 15pJ/b/chip inductive-coupling programmable bus for NAND flash memory stacking

Yasufumi Sugimori, Yoshinori Kohama, Mitsuko Saito, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    20 Citations (Scopus)
    Original languageEnglish
    Title of host publication2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2009
    DOIs
    Publication statusPublished - 2009 Sep 25
    Event2009 IEEE International Solid-State Circuits Conference ISSCC 2009 - San Francisco, CA, United States
    Duration: 2009 Feb 82009 Feb 12

    Publication series

    NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
    ISSN (Print)0193-6530

    Other

    Other2009 IEEE International Solid-State Circuits Conference ISSCC 2009
    CountryUnited States
    CitySan Francisco, CA
    Period09/2/809/2/12

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering

    Cite this

    Sugimori, Y., Kohama, Y., Saito, M., Yoshida, Y., Miura, N., Ishikuro, H., Sakurai, T., & Kuroda, T. (2009). A 2Gb/s 15pJ/b/chip inductive-coupling programmable bus for NAND flash memory stacking. In 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2009 [4977399] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). https://doi.org/10.1109/ISSCC.2009.4977399