Abstract
128 NAND Flash memory chips and 1 controller chip are stacked in a single package for SSD applications (Fig. 24.5.1). The controller chip accesses a random memory chip by relayed transmission using inductive-coupling transceivers [1,2]. A conventional terraced chip stacking scheme [1] requires spacer chips to provide bonding space. The total height would be 6.0mm. A spiral stair stacking scheme is proposed that requires no spacer chips. The total height is reduced to 3.9mm. Average communication distance is shortened, and transmission power is reduced to 60%. A coil of 1.1mm diameter, larger than conventional, is employed to extend the communication distance for enabling transmission relayed at every 8th chip. Number of transceivers activated for chip access is reduced to 1/4 compared to [1,2] where transmission was relayed at every 2nd chip with a coil of 0.2mm diameter. Although the transmission power needs to be increased by 3x in order to compensate for signal degradation due to eddy current, the transmission power is still reduced to 60% x (1/4) x 3 = 45%. Together with the reduction of the number of the activated receivers, energy consumption for the random access is reduced to 1.8pJ/b/chip which is 33% of [2]. The large coil is placed over memory core by using the third metal layer. Layout penalty is negligibly small, since the third metal is not utilized over the memory core other than reinforcing power supply in source lines. By placing the square coil diagonally to bit/word lines, capacitive/inductive interference between the chip access and memory read/write can be significantly reduced.
| Original language | English |
|---|---|
| Title of host publication | Digest of Technical Papers - IEEE International Solid-State Circuits Conference |
| Pages | 440-441 |
| Number of pages | 2 |
| Volume | 53 |
| DOIs | |
| Publication status | Published - 2010 |
| Event | 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - San Francisco, CA, United States Duration: 2010 Feb 7 → 2010 Feb 11 |
Other
| Other | 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 |
|---|---|
| Country | United States |
| City | San Francisco, CA |
| Period | 10/2/7 → 10/2/11 |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials
Cite this
A 2Gb/s 1.8pJ/b/chip inductive-coupling through-chip bus for 128-die NAND-flash memory stacking. / Saito, Mitsuko; Miura, Noriyuki; Kuroda, Tadahiro.
Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 53 2010. p. 440-441 5433929.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - A 2Gb/s 1.8pJ/b/chip inductive-coupling through-chip bus for 128-die NAND-flash memory stacking
AU - Saito, Mitsuko
AU - Miura, Noriyuki
AU - Kuroda, Tadahiro
PY - 2010
Y1 - 2010
N2 - 128 NAND Flash memory chips and 1 controller chip are stacked in a single package for SSD applications (Fig. 24.5.1). The controller chip accesses a random memory chip by relayed transmission using inductive-coupling transceivers [1,2]. A conventional terraced chip stacking scheme [1] requires spacer chips to provide bonding space. The total height would be 6.0mm. A spiral stair stacking scheme is proposed that requires no spacer chips. The total height is reduced to 3.9mm. Average communication distance is shortened, and transmission power is reduced to 60%. A coil of 1.1mm diameter, larger than conventional, is employed to extend the communication distance for enabling transmission relayed at every 8th chip. Number of transceivers activated for chip access is reduced to 1/4 compared to [1,2] where transmission was relayed at every 2nd chip with a coil of 0.2mm diameter. Although the transmission power needs to be increased by 3x in order to compensate for signal degradation due to eddy current, the transmission power is still reduced to 60% x (1/4) x 3 = 45%. Together with the reduction of the number of the activated receivers, energy consumption for the random access is reduced to 1.8pJ/b/chip which is 33% of [2]. The large coil is placed over memory core by using the third metal layer. Layout penalty is negligibly small, since the third metal is not utilized over the memory core other than reinforcing power supply in source lines. By placing the square coil diagonally to bit/word lines, capacitive/inductive interference between the chip access and memory read/write can be significantly reduced.
AB - 128 NAND Flash memory chips and 1 controller chip are stacked in a single package for SSD applications (Fig. 24.5.1). The controller chip accesses a random memory chip by relayed transmission using inductive-coupling transceivers [1,2]. A conventional terraced chip stacking scheme [1] requires spacer chips to provide bonding space. The total height would be 6.0mm. A spiral stair stacking scheme is proposed that requires no spacer chips. The total height is reduced to 3.9mm. Average communication distance is shortened, and transmission power is reduced to 60%. A coil of 1.1mm diameter, larger than conventional, is employed to extend the communication distance for enabling transmission relayed at every 8th chip. Number of transceivers activated for chip access is reduced to 1/4 compared to [1,2] where transmission was relayed at every 2nd chip with a coil of 0.2mm diameter. Although the transmission power needs to be increased by 3x in order to compensate for signal degradation due to eddy current, the transmission power is still reduced to 60% x (1/4) x 3 = 45%. Together with the reduction of the number of the activated receivers, energy consumption for the random access is reduced to 1.8pJ/b/chip which is 33% of [2]. The large coil is placed over memory core by using the third metal layer. Layout penalty is negligibly small, since the third metal is not utilized over the memory core other than reinforcing power supply in source lines. By placing the square coil diagonally to bit/word lines, capacitive/inductive interference between the chip access and memory read/write can be significantly reduced.
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U2 - 10.1109/ISSCC.2010.5433929
DO - 10.1109/ISSCC.2010.5433929
M3 - Conference contribution
AN - SCOPUS:77952174610
SN - 9781424460342
VL - 53
SP - 440
EP - 441
BT - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ER -