Abstract
This paper presents a 30 Gb/s/link 2.2 Tb/s/mm2 inductive-coupling link for a high-speed DRAM interface. The data rate per layout area is the highest among DRAM interfaces reported up to now. The proposed interface employs a high-speed injection-locking CDR technique that utilizes the derivative property of inductive coupling. Compared to conventional injection-locking CDR based on an XOR edge detector, the proposed technique doubles the operation speed and increases the data rate to 30 Gb/s/link. As a result, the data rate per layout area is increased to 2.2 Tb/s/mm2 , which is 2X that of the state-of-the-art inductive-coupling link, and 22X that of the state-of-the-art wired link.
| Original language | English |
|---|---|
| Article number | 5997296 |
| Pages (from-to) | 2552-2559 |
| Number of pages | 8 |
| Journal | IEEE Journal of Solid-State Circuits |
| Volume | 46 |
| Issue number | 11 |
| DOIs | |
| Publication status | Published - 2011 Nov |
Fingerprint
Keywords
- clock data recovery (CDR)
- DRAM
- Inductive coupling
- injection-locking
- three-dimensional
- wireless interconnect
ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
A 30 Gb/s/Link 2.2 Tb/s/mm2 inductively-coupled injection-locking CDR for high-speed DRAM interface. / Take, Yasuhiro; Miura, Noriyuki; Kuroda, Tadahiro.
In: IEEE Journal of Solid-State Circuits, Vol. 46, No. 11, 5997296, 11.2011, p. 2552-2559.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - A 30 Gb/s/Link 2.2 Tb/s/mm2 inductively-coupled injection-locking CDR for high-speed DRAM interface
AU - Take, Yasuhiro
AU - Miura, Noriyuki
AU - Kuroda, Tadahiro
PY - 2011/11
Y1 - 2011/11
N2 - This paper presents a 30 Gb/s/link 2.2 Tb/s/mm2 inductive-coupling link for a high-speed DRAM interface. The data rate per layout area is the highest among DRAM interfaces reported up to now. The proposed interface employs a high-speed injection-locking CDR technique that utilizes the derivative property of inductive coupling. Compared to conventional injection-locking CDR based on an XOR edge detector, the proposed technique doubles the operation speed and increases the data rate to 30 Gb/s/link. As a result, the data rate per layout area is increased to 2.2 Tb/s/mm2 , which is 2X that of the state-of-the-art inductive-coupling link, and 22X that of the state-of-the-art wired link.
AB - This paper presents a 30 Gb/s/link 2.2 Tb/s/mm2 inductive-coupling link for a high-speed DRAM interface. The data rate per layout area is the highest among DRAM interfaces reported up to now. The proposed interface employs a high-speed injection-locking CDR technique that utilizes the derivative property of inductive coupling. Compared to conventional injection-locking CDR based on an XOR edge detector, the proposed technique doubles the operation speed and increases the data rate to 30 Gb/s/link. As a result, the data rate per layout area is increased to 2.2 Tb/s/mm2 , which is 2X that of the state-of-the-art inductive-coupling link, and 22X that of the state-of-the-art wired link.
KW - clock data recovery (CDR)
KW - DRAM
KW - Inductive coupling
KW - injection-locking
KW - three-dimensional
KW - wireless interconnect
UR - http://www.scopus.com/inward/record.url?scp=80255136289&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=80255136289&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2011.2164023
DO - 10.1109/JSSC.2011.2164023
M3 - Article
VL - 46
SP - 2552
EP - 2559
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 11
M1 - 5997296
ER -