A 4-10 bit, 0.4-1V Power Supply, Power Scalable Asynchronous SAR-ADC in 40nm-CMOS withWide Supply Voltage Range SAR Controller

Akira Shikata; Ryota Sekimoto; Kentaro Yoshioka; Tadahiro Kuroda; Hiroki Ishikuro

doi:10.1587/transfun.E96.A.443

A 4-10 bit, 0.4-1V Power Supply, Power Scalable Asynchronous SAR-ADC in 40nm-CMOS withWide Supply Voltage Range SAR Controller

Akira Shikata, Ryota Sekimoto, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro

Department of Electronics and Electrical Engineering

Research output: Contribution to journal › Article › peer-review

3 Citations (Scopus)

Abstract

This paper presents a wide range in supply voltage, resolution, and sampling rate asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). The proposed differential flipflop in SAR logic and high efficiency wide range delay element extend the flexibility of speed and resolution tradeoff. The ADC fabricated in 40 nm CMOS process covers 4-10 bit resolution and 0.4-1V power supply range. The ADC achieved 49.8 dB SNDR and the peak FoM of 3.4 fJ/conv. with 160 kS/sec at 0.4V single power supply voltage. At 10 bit mode and 1V operation, up to 10MS/s, the FoM is below 10 fJ/conv. while keeping ENOB of 8.7 bit.

Original language	English
Pages (from-to)	443-452
Number of pages	10
Journal	IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Volume	E96-A
Issue number	2
DOIs	https://doi.org/10.1587/transfun.E96.A.443
Publication status	Published - 2013 Feb

Keywords

Analog-to-digital converter
Asynchronous
Differential flip-flop
Successive approximation

ASJC Scopus subject areas

Signal Processing
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering
Applied Mathematics

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10.1587/transfun.E96.A.443

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A 4-10 bit, 0.4-1V Power Supply, Power Scalable Asynchronous SAR-ADC in 40nm-CMOS withWide Supply Voltage Range SAR Controller. / Shikata, Akira; Sekimoto, Ryota; Yoshioka, Kentaro et al.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E96-A, No. 2, 02.2013, p. 443-452.

Research output: Contribution to journal › Article › peer-review

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AU - Kuroda, Tadahiro

AU - Ishikuro, Hiroki

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AB - This paper presents a wide range in supply voltage, resolution, and sampling rate asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). The proposed differential flipflop in SAR logic and high efficiency wide range delay element extend the flexibility of speed and resolution tradeoff. The ADC fabricated in 40 nm CMOS process covers 4-10 bit resolution and 0.4-1V power supply range. The ADC achieved 49.8 dB SNDR and the peak FoM of 3.4 fJ/conv. with 160 kS/sec at 0.4V single power supply voltage. At 10 bit mode and 1V operation, up to 10MS/s, the FoM is below 10 fJ/conv. while keeping ENOB of 8.7 bit.

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A 4-10 bit, 0.4-1V Power Supply, Power Scalable Asynchronous SAR-ADC in 40nm-CMOS withWide Supply Voltage Range SAR Controller

Abstract

Keywords

ASJC Scopus subject areas

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