A 4-10 bit, 0.4-1V Power Supply, Power Scalable Asynchronous SAR-ADC in 40nm-CMOS withWide Supply Voltage Range SAR Controller

Akira Shikata, Ryota Sekimoto, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

This paper presents a wide range in supply voltage, resolution, and sampling rate asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). The proposed differential flipflop in SAR logic and high efficiency wide range delay element extend the flexibility of speed and resolution tradeoff. The ADC fabricated in 40 nm CMOS process covers 4-10 bit resolution and 0.4-1V power supply range. The ADC achieved 49.8 dB SNDR and the peak FoM of 3.4 fJ/conv. with 160 kS/sec at 0.4V single power supply voltage. At 10 bit mode and 1V operation, up to 10MS/s, the FoM is below 10 fJ/conv. while keeping ENOB of 8.7 bit.

Original languageEnglish
Pages (from-to)443-452
Number of pages10
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE96-A
Issue number2
DOIs
Publication statusPublished - 2013 Feb

Fingerprint

Analog-to-digital Converter
Successive Approximation
Digital to analog conversion
Voltage
Controller
Controllers
Electric potential
Range of data
High Efficiency
Trade-offs
Flexibility
Cover
Logic
Sampling

Keywords

  • Analog-to-digital converter
  • Asynchronous
  • Differential flip-flop
  • Successive approximation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Graphics and Computer-Aided Design
  • Applied Mathematics
  • Signal Processing

Cite this

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abstract = "This paper presents a wide range in supply voltage, resolution, and sampling rate asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). The proposed differential flipflop in SAR logic and high efficiency wide range delay element extend the flexibility of speed and resolution tradeoff. The ADC fabricated in 40 nm CMOS process covers 4-10 bit resolution and 0.4-1V power supply range. The ADC achieved 49.8 dB SNDR and the peak FoM of 3.4 fJ/conv. with 160 kS/sec at 0.4V single power supply voltage. At 10 bit mode and 1V operation, up to 10MS/s, the FoM is below 10 fJ/conv. while keeping ENOB of 8.7 bit.",
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author = "Akira Shikata and Ryota Sekimoto and Kentaro Yoshioka and Tadahiro Kuroda and Hiroki Ishikuro",
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AU - Yoshioka, Kentaro

AU - Kuroda, Tadahiro

AU - Ishikuro, Hiroki

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