Abstract
This paper presents a wide range in supply voltage, resolution, and sampling rate asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). The proposed differential flipflop in SAR logic and high efficiency wide range delay element extend the flexibility of speed and resolution tradeoff. The ADC fabricated in 40 nm CMOS process covers 4-10 bit resolution and 0.4-1V power supply range. The ADC achieved 49.8 dB SNDR and the peak FoM of 3.4 fJ/conv. with 160 kS/sec at 0.4V single power supply voltage. At 10 bit mode and 1V operation, up to 10MS/s, the FoM is below 10 fJ/conv. while keeping ENOB of 8.7 bit.
| Original language | English |
|---|---|
| Pages (from-to) | 443-452 |
| Number of pages | 10 |
| Journal | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |
| Volume | E96-A |
| Issue number | 2 |
| DOIs | |
| Publication status | Published - 2013 Feb |
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Keywords
- Analog-to-digital converter
- Asynchronous
- Differential flip-flop
- Successive approximation
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Computer Graphics and Computer-Aided Design
- Applied Mathematics
- Signal Processing
Cite this
A 4-10 bit, 0.4-1V Power Supply, Power Scalable Asynchronous SAR-ADC in 40nm-CMOS withWide Supply Voltage Range SAR Controller. / Shikata, Akira; Sekimoto, Ryota; Yoshioka, Kentaro; Kuroda, Tadahiro; Ishikuro, Hiroki.
In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E96-A, No. 2, 02.2013, p. 443-452.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - A 4-10 bit, 0.4-1V Power Supply, Power Scalable Asynchronous SAR-ADC in 40nm-CMOS withWide Supply Voltage Range SAR Controller
AU - Shikata, Akira
AU - Sekimoto, Ryota
AU - Yoshioka, Kentaro
AU - Kuroda, Tadahiro
AU - Ishikuro, Hiroki
PY - 2013/2
Y1 - 2013/2
N2 - This paper presents a wide range in supply voltage, resolution, and sampling rate asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). The proposed differential flipflop in SAR logic and high efficiency wide range delay element extend the flexibility of speed and resolution tradeoff. The ADC fabricated in 40 nm CMOS process covers 4-10 bit resolution and 0.4-1V power supply range. The ADC achieved 49.8 dB SNDR and the peak FoM of 3.4 fJ/conv. with 160 kS/sec at 0.4V single power supply voltage. At 10 bit mode and 1V operation, up to 10MS/s, the FoM is below 10 fJ/conv. while keeping ENOB of 8.7 bit.
AB - This paper presents a wide range in supply voltage, resolution, and sampling rate asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). The proposed differential flipflop in SAR logic and high efficiency wide range delay element extend the flexibility of speed and resolution tradeoff. The ADC fabricated in 40 nm CMOS process covers 4-10 bit resolution and 0.4-1V power supply range. The ADC achieved 49.8 dB SNDR and the peak FoM of 3.4 fJ/conv. with 160 kS/sec at 0.4V single power supply voltage. At 10 bit mode and 1V operation, up to 10MS/s, the FoM is below 10 fJ/conv. while keeping ENOB of 8.7 bit.
KW - Analog-to-digital converter
KW - Asynchronous
KW - Differential flip-flop
KW - Successive approximation
UR - http://www.scopus.com/inward/record.url?scp=84873327164&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84873327164&partnerID=8YFLogxK
U2 - 10.1587/transfun.E96.A.443
DO - 10.1587/transfun.E96.A.443
M3 - Article
AN - SCOPUS:84873327164
VL - E96-A
SP - 443
EP - 452
JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
SN - 0916-8508
IS - 2
ER -