A 40-44 Gb/s 3 × oversampling CMOS CDR/1: 16 DEMUX

Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker

Research output: Contribution to journalArticle

20 Citations (Scopus)

Abstract

A CMOS CDR and 1:16 demux fabricated in a low-cost 90 nm bulk CMOS process operates at 40-44 Gb/s and dissipates 910 mW. A quarter-rate hybrid phase-tracking/3 × blind-oversampling architecture is used to improve jitter tolerance, reduce the need for high-power CML circuits, and enable frequency acquisition without a reference clock. Input data are sampled using a 24-phase distributed VCO, and a digital CDR recovers 16 bits and a 2.5 GHz clock from 48 demultiplexed samples spanning 16 UI. Conformance to the ITU-T G.8251 jitter tolerance mask (BER < 10-12 with a 231-1 PRBS source) is demonstrated using both an on-chip and an external BERT.

Original languageEnglish
Article number4381457
Pages (from-to)2726-2735
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume42
Issue number12
DOIs
Publication statusPublished - 2007 Dec

Fingerprint

Jitter
Clocks
Emitter coupled logic circuits
Variable frequency oscillators
Masks
Networks (circuits)
Costs

Keywords

  • Clock and data recovery (CDR)
  • CML
  • CMOS
  • Delay line
  • Demultiplexer
  • Distributed circuits
  • Distributed VCO
  • Hybrid CDR
  • Jitter tolerance
  • Optical communications
  • Oversam-pling
  • Serializer-deserializer

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Nedovic, N., Tzartzanis, N., Tamura, H., Rotella, F. M., Wiklund, M., Mizutani, Y., ... Walker, W. W. (2007). A 40-44 Gb/s 3 × oversampling CMOS CDR/1: 16 DEMUX. IEEE Journal of Solid-State Circuits, 42(12), 2726-2735. [4381457]. https://doi.org/10.1109/JSSC.2007.908714

A 40-44 Gb/s 3 × oversampling CMOS CDR/1 : 16 DEMUX. / Nedovic, Nikola; Tzartzanis, Nestoras; Tamura, Hirotaka; Rotella, Francis M.; Wiklund, Magnus; Mizutani, Yuma; Okaniwa, Yusuke; Kuroda, Tadahiro; Ogawa, Junji; Walker, William W.

In: IEEE Journal of Solid-State Circuits, Vol. 42, No. 12, 4381457, 12.2007, p. 2726-2735.

Research output: Contribution to journalArticle

Nedovic, N, Tzartzanis, N, Tamura, H, Rotella, FM, Wiklund, M, Mizutani, Y, Okaniwa, Y, Kuroda, T, Ogawa, J & Walker, WW 2007, 'A 40-44 Gb/s 3 × oversampling CMOS CDR/1: 16 DEMUX', IEEE Journal of Solid-State Circuits, vol. 42, no. 12, 4381457, pp. 2726-2735. https://doi.org/10.1109/JSSC.2007.908714
Nedovic N, Tzartzanis N, Tamura H, Rotella FM, Wiklund M, Mizutani Y et al. A 40-44 Gb/s 3 × oversampling CMOS CDR/1: 16 DEMUX. IEEE Journal of Solid-State Circuits. 2007 Dec;42(12):2726-2735. 4381457. https://doi.org/10.1109/JSSC.2007.908714
Nedovic, Nikola ; Tzartzanis, Nestoras ; Tamura, Hirotaka ; Rotella, Francis M. ; Wiklund, Magnus ; Mizutani, Yuma ; Okaniwa, Yusuke ; Kuroda, Tadahiro ; Ogawa, Junji ; Walker, William W. / A 40-44 Gb/s 3 × oversampling CMOS CDR/1 : 16 DEMUX. In: IEEE Journal of Solid-State Circuits. 2007 ; Vol. 42, No. 12. pp. 2726-2735.
@article{f2866015b0194fb2947c9c936eb80857,
title = "A 40-44 Gb/s 3 × oversampling CMOS CDR/1: 16 DEMUX",
abstract = "A CMOS CDR and 1:16 demux fabricated in a low-cost 90 nm bulk CMOS process operates at 40-44 Gb/s and dissipates 910 mW. A quarter-rate hybrid phase-tracking/3 × blind-oversampling architecture is used to improve jitter tolerance, reduce the need for high-power CML circuits, and enable frequency acquisition without a reference clock. Input data are sampled using a 24-phase distributed VCO, and a digital CDR recovers 16 bits and a 2.5 GHz clock from 48 demultiplexed samples spanning 16 UI. Conformance to the ITU-T G.8251 jitter tolerance mask (BER < 10-12 with a 231-1 PRBS source) is demonstrated using both an on-chip and an external BERT.",
keywords = "Clock and data recovery (CDR), CML, CMOS, Delay line, Demultiplexer, Distributed circuits, Distributed VCO, Hybrid CDR, Jitter tolerance, Optical communications, Oversam-pling, Serializer-deserializer",
author = "Nikola Nedovic and Nestoras Tzartzanis and Hirotaka Tamura and Rotella, {Francis M.} and Magnus Wiklund and Yuma Mizutani and Yusuke Okaniwa and Tadahiro Kuroda and Junji Ogawa and Walker, {William W.}",
year = "2007",
month = "12",
doi = "10.1109/JSSC.2007.908714",
language = "English",
volume = "42",
pages = "2726--2735",
journal = "IEEE Journal of Solid-State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "12",

}

TY - JOUR

T1 - A 40-44 Gb/s 3 × oversampling CMOS CDR/1

T2 - 16 DEMUX

AU - Nedovic, Nikola

AU - Tzartzanis, Nestoras

AU - Tamura, Hirotaka

AU - Rotella, Francis M.

AU - Wiklund, Magnus

AU - Mizutani, Yuma

AU - Okaniwa, Yusuke

AU - Kuroda, Tadahiro

AU - Ogawa, Junji

AU - Walker, William W.

PY - 2007/12

Y1 - 2007/12

N2 - A CMOS CDR and 1:16 demux fabricated in a low-cost 90 nm bulk CMOS process operates at 40-44 Gb/s and dissipates 910 mW. A quarter-rate hybrid phase-tracking/3 × blind-oversampling architecture is used to improve jitter tolerance, reduce the need for high-power CML circuits, and enable frequency acquisition without a reference clock. Input data are sampled using a 24-phase distributed VCO, and a digital CDR recovers 16 bits and a 2.5 GHz clock from 48 demultiplexed samples spanning 16 UI. Conformance to the ITU-T G.8251 jitter tolerance mask (BER < 10-12 with a 231-1 PRBS source) is demonstrated using both an on-chip and an external BERT.

AB - A CMOS CDR and 1:16 demux fabricated in a low-cost 90 nm bulk CMOS process operates at 40-44 Gb/s and dissipates 910 mW. A quarter-rate hybrid phase-tracking/3 × blind-oversampling architecture is used to improve jitter tolerance, reduce the need for high-power CML circuits, and enable frequency acquisition without a reference clock. Input data are sampled using a 24-phase distributed VCO, and a digital CDR recovers 16 bits and a 2.5 GHz clock from 48 demultiplexed samples spanning 16 UI. Conformance to the ITU-T G.8251 jitter tolerance mask (BER < 10-12 with a 231-1 PRBS source) is demonstrated using both an on-chip and an external BERT.

KW - Clock and data recovery (CDR)

KW - CML

KW - CMOS

KW - Delay line

KW - Demultiplexer

KW - Distributed circuits

KW - Distributed VCO

KW - Hybrid CDR

KW - Jitter tolerance

KW - Optical communications

KW - Oversam-pling

KW - Serializer-deserializer

UR - http://www.scopus.com/inward/record.url?scp=53949105775&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=53949105775&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2007.908714

DO - 10.1109/JSSC.2007.908714

M3 - Article

AN - SCOPUS:53949105775

VL - 42

SP - 2726

EP - 2735

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 12

M1 - 4381457

ER -