A 40-44 Gb/s 3 × oversampling CMOS CDR/1:16 DEMUX

Nikola Nedovic; Nestoras Tzartzanis; Hirotaka Tamura; Francis M. Rotella; Magnus Wiklund; Yuma Mizutani; Yusuke Okaniwa; Tadahiro Kuroda; Junji Ogawa; William W. Walker

doi:10.1109/JSSC.2007.908714

A 40-44 Gb/s 3 × oversampling CMOS CDR/1:16 DEMUX

Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker

Research output: Contribution to journal › Article › peer-review

20 Citations (Scopus)

Abstract

A CMOS CDR and 1:16 demux fabricated in a low-cost 90 nm bulk CMOS process operates at 40-44 Gb/s and dissipates 910 mW. A quarter-rate hybrid phase-tracking/3 × blind-oversampling architecture is used to improve jitter tolerance, reduce the need for high-power CML circuits, and enable frequency acquisition without a reference clock. Input data are sampled using a 24-phase distributed VCO, and a digital CDR recovers 16 bits and a 2.5 GHz clock from 48 demultiplexed samples spanning 16 UI. Conformance to the ITU-T G.8251 jitter tolerance mask (BER < 10^-12 with a 2³¹-1 PRBS source) is demonstrated using both an on-chip and an external BERT.

Original language	English
Article number	4381457
Pages (from-to)	2726-2735
Number of pages	10
Journal	IEEE Journal of Solid-State Circuits
Volume	42
Issue number	12
DOIs	https://doi.org/10.1109/JSSC.2007.908714
Publication status	Published - 2007 Dec 1

Keywords

CML
CMOS
Clock and data recovery (CDR)
Delay line
Demultiplexer
Distributed VCO
Distributed circuits
Hybrid CDR
Jitter tolerance
Optical communications
Oversam-pling
Serializer-deserializer

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/JSSC.2007.908714

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Cite this

A 40-44 Gb/s 3 × oversampling CMOS CDR/1:16 DEMUX. / Nedovic, Nikola; Tzartzanis, Nestoras; Tamura, Hirotaka; Rotella, Francis M.; Wiklund, Magnus; Mizutani, Yuma; Okaniwa, Yusuke; Kuroda, Tadahiro; Ogawa, Junji; Walker, William W.

In: IEEE Journal of Solid-State Circuits, Vol. 42, No. 12, 4381457, 01.12.2007, p. 2726-2735.

Research output: Contribution to journal › Article › peer-review

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abstract = "A CMOS CDR and 1:16 demux fabricated in a low-cost 90 nm bulk CMOS process operates at 40-44 Gb/s and dissipates 910 mW. A quarter-rate hybrid phase-tracking/3 × blind-oversampling architecture is used to improve jitter tolerance, reduce the need for high-power CML circuits, and enable frequency acquisition without a reference clock. Input data are sampled using a 24-phase distributed VCO, and a digital CDR recovers 16 bits and a 2.5 GHz clock from 48 demultiplexed samples spanning 16 UI. Conformance to the ITU-T G.8251 jitter tolerance mask (BER < 10-12 with a 231-1 PRBS source) is demonstrated using both an on-chip and an external BERT.",

keywords = "CML, CMOS, Clock and data recovery (CDR), Delay line, Demultiplexer, Distributed VCO, Distributed circuits, Hybrid CDR, Jitter tolerance, Optical communications, Oversam-pling, Serializer-deserializer",

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AU - Wiklund, Magnus

AU - Mizutani, Yuma

AU - Okaniwa, Yusuke

AU - Kuroda, Tadahiro

AU - Ogawa, Junji

AU - Walker, William W.

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