A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique

Yusuke Okaniwa, Hirotaka Tamura, Masaya Kibune, Daisuke Yamazaki, Tsz Shing Cheung, Junji Ogawa, Nestoras Tzartzanis, William W. Walker, Tadahiro Kuroda

    Research output: Contribution to journalArticle

    36 Citations (Scopus)

    Abstract

    A differential comparator that can sample 40-Gb/s signals and that operates off a single 1.2-V supply was designed and fabricated in 0.11-μm standard CMOS technology. It consists of a front-end sampler, a regenerative stage, and a clocked amplifier to provide a small aperture time and a high toggle rate. The clocked amplifier employs a bandwidth modulation technique that switches the feedback gain to reduce the reset time while keeping the effective gain high. We confirmed that the comparator receives a 40-Gb/s data stream at a toggle rate of 10 GHz with bit error rate less than 10 -12 by laboratory measurements.

    Original languageEnglish
    Pages (from-to)1680-1686
    Number of pages7
    JournalIEEE Journal of Solid-State Circuits
    Volume40
    Issue number8
    DOIs
    Publication statusPublished - 2005 Aug 1

    Keywords

    • CMOS integrated circuits
    • Comparators
    • High-speed integrated circuits

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

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  • Cite this

    Okaniwa, Y., Tamura, H., Kibune, M., Yamazaki, D., Cheung, T. S., Ogawa, J., Tzartzanis, N., Walker, W. W., & Kuroda, T. (2005). A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique. IEEE Journal of Solid-State Circuits, 40(8), 1680-1686. https://doi.org/10.1109/JSSC.2005.852014