A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique

Yusuke Okaniwa, Hirotaka Tamura, Masaya Kibune, Daisuke Yamazaki, Tsz Shing Cheung, Junji Ogawa, Nestoras Tzartzanis, William W. Walker, Tadahiro Kuroda

Research output: Contribution to journalArticle

32 Citations (Scopus)

Abstract

A differential comparator that can sample 40-Gb/s signals and that operates off a single 1.2-V supply was designed and fabricated in 0.11-μm standard CMOS technology. It consists of a front-end sampler, a regenerative stage, and a clocked amplifier to provide a small aperture time and a high toggle rate. The clocked amplifier employs a bandwidth modulation technique that switches the feedback gain to reduce the reset time while keeping the effective gain high. We confirmed that the comparator receives a 40-Gb/s data stream at a toggle rate of 10 GHz with bit error rate less than 10 -12 by laboratory measurements.

Original languageEnglish
Pages (from-to)1680-1686
Number of pages7
JournalIEEE Journal of Solid-State Circuits
Volume40
Issue number8
DOIs
Publication statusPublished - 2005 Aug

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Modulation
Bandwidth
Bit error rate
Switches
Feedback

Keywords

  • CMOS integrated circuits
  • Comparators
  • High-speed integrated circuits

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique. / Okaniwa, Yusuke; Tamura, Hirotaka; Kibune, Masaya; Yamazaki, Daisuke; Cheung, Tsz Shing; Ogawa, Junji; Tzartzanis, Nestoras; Walker, William W.; Kuroda, Tadahiro.

In: IEEE Journal of Solid-State Circuits, Vol. 40, No. 8, 08.2005, p. 1680-1686.

Research output: Contribution to journalArticle

Okaniwa, Y, Tamura, H, Kibune, M, Yamazaki, D, Cheung, TS, Ogawa, J, Tzartzanis, N, Walker, WW & Kuroda, T 2005, 'A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique', IEEE Journal of Solid-State Circuits, vol. 40, no. 8, pp. 1680-1686. https://doi.org/10.1109/JSSC.2005.852014
Okaniwa Y, Tamura H, Kibune M, Yamazaki D, Cheung TS, Ogawa J et al. A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique. IEEE Journal of Solid-State Circuits. 2005 Aug;40(8):1680-1686. https://doi.org/10.1109/JSSC.2005.852014
Okaniwa, Yusuke ; Tamura, Hirotaka ; Kibune, Masaya ; Yamazaki, Daisuke ; Cheung, Tsz Shing ; Ogawa, Junji ; Tzartzanis, Nestoras ; Walker, William W. ; Kuroda, Tadahiro. / A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique. In: IEEE Journal of Solid-State Circuits. 2005 ; Vol. 40, No. 8. pp. 1680-1686.
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