A 40-to-44Gb/s 3× oversampling CMOS CDR/1:16 DEMUX

Nikola Nedovic; Nestoras Tzartzanis; Hirotaka Tamura; Francis Rotella; Magnus Wiklund; Yuma Mizutani; Yusuke Okanlwa; Tadahiro Kuroda; Junji Ogawa; William Walker

doi:10.1109/ISSCC.2007.373375

A 40-to-44Gb/s 3× oversampling CMOS CDR/1:16 DEMUX

Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okanlwa, Tadahiro Kuroda, Junji Ogawa, William Walker

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

8 Citations (Scopus)

Abstract

A 3× oversampling CDR and 1:16 DEWUX occupies 0.8×1.8mm ² in a 90nm CMOS process. The chip operates at 40 to 44Gb/s and dissipates 0 91W. Input data is sampled using a 24-phase distributed VCO and a digital CDR recovers 16 bits and a 2.5GHz clock from 48 demultiplexed samples spanning 16UI. Conformance to the ITU G.8251 jitter tolerance mask (BER <10^-12 with a 2³¹-1 PRBS source) is demonstrated.

Original language	English
Title of host publication	2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	224-226
Number of pages	3
ISBN (Print)	1424408539, 9781424408535
DOIs	https://doi.org/10.1109/ISSCC.2007.373375
Publication status	Published - 2007
Event	54th IEEE International Solid-State Circuits Conference, ISSCC 2007 - San Francisco, CA, United States Duration: 2007 Feb 11 → 2007 Feb 15

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)	0193-6530

Other

Other	54th IEEE International Solid-State Circuits Conference, ISSCC 2007
Country/Territory	United States
City	San Francisco, CA
Period	07/2/11 → 07/2/15

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/ISSCC.2007.373375

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Nedovic, N., Tzartzanis, N., Tamura, H., Rotella, F., Wiklund, M., Mizutani, Y., Okanlwa, Y., Kuroda, T., Ogawa, J., & Walker, W. (2007). A 40-to-44Gb/s 3× oversampling CMOS CDR/1:16 DEMUX. In 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers (pp. 224-226). [4242346] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2007.373375

A 40-to-44Gb/s 3× oversampling CMOS CDR/1:16 DEMUX. / Nedovic, Nikola; Tzartzanis, Nestoras; Tamura, Hirotaka et al.

2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2007. p. 224-226 4242346 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Nedovic, N, Tzartzanis, N, Tamura, H, Rotella, F, Wiklund, M, Mizutani, Y, Okanlwa, Y, Kuroda, T, Ogawa, J & Walker, W 2007, A 40-to-44Gb/s 3× oversampling CMOS CDR/1:16 DEMUX. in 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers., 4242346, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Institute of Electrical and Electronics Engineers Inc., pp. 224-226, 54th IEEE International Solid-State Circuits Conference, ISSCC 2007, San Francisco, CA, United States, 07/2/11. https://doi.org/10.1109/ISSCC.2007.373375

Nedovic N, Tzartzanis N, Tamura H, Rotella F, Wiklund M, Mizutani Y et al. A 40-to-44Gb/s 3× oversampling CMOS CDR/1:16 DEMUX. In 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2007. p. 224-226. 4242346. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC.2007.373375

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abstract = "A 3× oversampling CDR and 1:16 DEWUX occupies 0.8×1.8mm 2 in a 90nm CMOS process. The chip operates at 40 to 44Gb/s and dissipates 0 91W. Input data is sampled using a 24-phase distributed VCO and a digital CDR recovers 16 bits and a 2.5GHz clock from 48 demultiplexed samples spanning 16UI. Conformance to the ITU G.8251 jitter tolerance mask (BER <10-12 with a 231-1 PRBS source) is demonstrated.",

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AU - Wiklund, Magnus

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AB - A 3× oversampling CDR and 1:16 DEWUX occupies 0.8×1.8mm 2 in a 90nm CMOS process. The chip operates at 40 to 44Gb/s and dissipates 0 91W. Input data is sampled using a 24-phase distributed VCO and a digital CDR recovers 16 bits and a 2.5GHz clock from 48 demultiplexed samples spanning 16UI. Conformance to the ITU G.8251 jitter tolerance mask (BER <10-12 with a 231-1 PRBS source) is demonstrated.

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A 40-to-44Gb/s 3× oversampling CMOS CDR/1:16 DEMUX

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