A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator

Ryota Sekimoto, Akira Shikata, Tadahiro Kuroda, Hiroki Ishikuro

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

This paper presents an ultra low power and low voltage successive- approximation-register (SAR) analog-to-digital converter (ADC) that uses an adaptive timing optimized asynchronous clock generator. Compared to asynchronous converters that use the conventional clock generator, the frequency range is expanded by 50% at 0.4V analog and 0.7V digital power supply voltage. By calibrating the delay time of the clock generator, the DAC settling time is optimized to counter the device mismatch. Test chip has been fabricated in 40nm standard CMOS process and achieved figure of merit (FoM) of 8.75-fJ/conversion- step with 2.048MS/s at 0.6V analog and 0.7V digital power supply voltage. The ADC operates from 50S/s to 8MS/s performing over 7.5-ENOB.

Original languageEnglish
Title of host publicationESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference
Pages471-474
Number of pages4
DOIs
Publication statusPublished - 2011 Dec 12
Event37th European Solid-State Circuits Conference, ESSCIRC 2011 - Helsinki, Finland
Duration: 2011 Sep 122011 Sep 16

Publication series

NameEuropean Solid-State Circuits Conference
ISSN (Print)1930-8833

Other

Other37th European Solid-State Circuits Conference, ESSCIRC 2011
CountryFinland
CityHelsinki
Period11/9/1211/9/16

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Sekimoto, R., Shikata, A., Kuroda, T., & Ishikuro, H. (2011). A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator. In ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference (pp. 471-474). [6045009] (European Solid-State Circuits Conference). https://doi.org/10.1109/ESSCIRC.2011.6045009