A 40nm CMOS full asynchronous nano-watt SAR ADC with 98% leakage power reduction by boosted self power gating

Ryota Sekimoto; Akira Shikata; Kentaro Yoshioka; Tadahiro Kuroda; Hiroki Ishikuro

doi:10.1109/IPEC.2012.6522650

A 40nm CMOS full asynchronous nano-watt SAR ADC with 98% leakage power reduction by boosted self power gating

Ryota Sekimoto, Akira Shikata, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro

Department of Electronics and Electrical Engineering

Research output: Contribution to conference › Paper

Abstract

This paper presents an ultra low power and ultra low voltage SAR ADC. Full asynchronous operation and boosted self power gating are proposed to improve conversion accuracy and reduce static leakage power. Test chip fabricated in 40nm CMOS process has successfully reduced leakage power by 98% and it performs ENOB of 8.2bit and consumes only 0.65nW with 0.1kS/s at 0.5V. The power consumption is scalable up to 4MS/s and power supply range from 0.4 to 0.7V. The best figure of merit (FoM) of 5.2fJ/conversion-step was obtained with 20kS/s at 0.5V.

Original language	English
Pages	161-164
Number of pages	4
DOIs	https://doi.org/10.1109/IPEC.2012.6522650
Publication status	Published - 2012 Dec 1
Event	2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 - Kobe, Japan Duration: 2012 Nov 12 → 2012 Nov 14

Other

Other	2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012
Country	Japan
City	Kobe
Period	12/11/12 → 12/11/14

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ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Cite this

Sekimoto, R., Shikata, A., Yoshioka, K., Kuroda, T., & Ishikuro, H. (2012). A 40nm CMOS full asynchronous nano-watt SAR ADC with 98% leakage power reduction by boosted self power gating. 161-164. Paper presented at 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012, Kobe, Japan. https://doi.org/10.1109/IPEC.2012.6522650

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Access to Document

10.1109/IPEC.2012.6522650