A 40nm CMOS full asynchronous nano-watt SAR ADC with 98% leakage power reduction by boosted self power gating

Ryota Sekimoto, Akira Shikata, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro

    Research output: Contribution to conferencePaper

    4 Citations (Scopus)

    Abstract

    This paper presents an ultra low power and ultra low voltage SAR ADC. Full asynchronous operation and boosted self power gating are proposed to improve conversion accuracy and reduce static leakage power. Test chip fabricated in 40nm CMOS process has successfully reduced leakage power by 98% and it performs ENOB of 8.2bit and consumes only 0.65nW with 0.1kS/s at 0.5V. The power consumption is scalable up to 4MS/s and power supply range from 0.4 to 0.7V. The best figure of merit (FoM) of 5.2fJ/conversion-step was obtained with 20kS/s at 0.5V.

    Original languageEnglish
    Pages161-164
    Number of pages4
    DOIs
    Publication statusPublished - 2012 Dec 1
    Event2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 - Kobe, Japan
    Duration: 2012 Nov 122012 Nov 14

    Other

    Other2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012
    CountryJapan
    CityKobe
    Period12/11/1212/11/14

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

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  • Cite this

    Sekimoto, R., Shikata, A., Yoshioka, K., Kuroda, T., & Ishikuro, H. (2012). A 40nm CMOS full asynchronous nano-watt SAR ADC with 98% leakage power reduction by boosted self power gating. 161-164. Paper presented at 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012, Kobe, Japan. https://doi.org/10.1109/IPEC.2012.6522650