A 40nm CMOS full asynchronous nano-watt SAR ADC with 98% leakage power reduction by boosted self power gating

Ryota Sekimoto; Akira Shikata; Kentaro Yoshioka; Tadahiro Kuroda; Hiroki Ishikuro

doi:10.1109/IPEC.2012.6522650

A 40nm CMOS full asynchronous nano-watt SAR ADC with 98% leakage power reduction by boosted self power gating

Ryota Sekimoto, Akira Shikata, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro

Department of Electronics and Electrical Engineering

Research output: Contribution to conference › Paper › peer-review

4 Citations (Scopus)

Abstract

This paper presents an ultra low power and ultra low voltage SAR ADC. Full asynchronous operation and boosted self power gating are proposed to improve conversion accuracy and reduce static leakage power. Test chip fabricated in 40nm CMOS process has successfully reduced leakage power by 98% and it performs ENOB of 8.2bit and consumes only 0.65nW with 0.1kS/s at 0.5V. The power consumption is scalable up to 4MS/s and power supply range from 0.4 to 0.7V. The best figure of merit (FoM) of 5.2fJ/conversion-step was obtained with 20kS/s at 0.5V.

Original language	English
Pages	161-164
Number of pages	4
DOIs	https://doi.org/10.1109/IPEC.2012.6522650
Publication status	Published - 2012 Dec 1
Event	2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 - Kobe, Japan Duration: 2012 Nov 12 → 2012 Nov 14

Other

Other	2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012
Country/Territory	Japan
City	Kobe
Period	12/11/12 → 12/11/14

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/IPEC.2012.6522650

Cite this

@conference{951c9fed582542a09f6da1adacad52f2,

title = "A 40nm CMOS full asynchronous nano-watt SAR ADC with 98% leakage power reduction by boosted self power gating",

abstract = "This paper presents an ultra low power and ultra low voltage SAR ADC. Full asynchronous operation and boosted self power gating are proposed to improve conversion accuracy and reduce static leakage power. Test chip fabricated in 40nm CMOS process has successfully reduced leakage power by 98% and it performs ENOB of 8.2bit and consumes only 0.65nW with 0.1kS/s at 0.5V. The power consumption is scalable up to 4MS/s and power supply range from 0.4 to 0.7V. The best figure of merit (FoM) of 5.2fJ/conversion-step was obtained with 20kS/s at 0.5V.",

author = "Ryota Sekimoto and Akira Shikata and Kentaro Yoshioka and Tadahiro Kuroda and Hiroki Ishikuro",

year = "2012",

month = dec,

day = "1",

doi = "10.1109/IPEC.2012.6522650",

language = "English",

pages = "161--164",

note = "2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 ; Conference date: 12-11-2012 Through 14-11-2012",

}

TY - CONF

T1 - A 40nm CMOS full asynchronous nano-watt SAR ADC with 98% leakage power reduction by boosted self power gating

AU - Sekimoto, Ryota

AU - Shikata, Akira

AU - Yoshioka, Kentaro

AU - Kuroda, Tadahiro

AU - Ishikuro, Hiroki

PY - 2012/12/1

Y1 - 2012/12/1

N2 - This paper presents an ultra low power and ultra low voltage SAR ADC. Full asynchronous operation and boosted self power gating are proposed to improve conversion accuracy and reduce static leakage power. Test chip fabricated in 40nm CMOS process has successfully reduced leakage power by 98% and it performs ENOB of 8.2bit and consumes only 0.65nW with 0.1kS/s at 0.5V. The power consumption is scalable up to 4MS/s and power supply range from 0.4 to 0.7V. The best figure of merit (FoM) of 5.2fJ/conversion-step was obtained with 20kS/s at 0.5V.

AB - This paper presents an ultra low power and ultra low voltage SAR ADC. Full asynchronous operation and boosted self power gating are proposed to improve conversion accuracy and reduce static leakage power. Test chip fabricated in 40nm CMOS process has successfully reduced leakage power by 98% and it performs ENOB of 8.2bit and consumes only 0.65nW with 0.1kS/s at 0.5V. The power consumption is scalable up to 4MS/s and power supply range from 0.4 to 0.7V. The best figure of merit (FoM) of 5.2fJ/conversion-step was obtained with 20kS/s at 0.5V.

UR - http://www.scopus.com/inward/record.url?scp=84881047279&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84881047279&partnerID=8YFLogxK

U2 - 10.1109/IPEC.2012.6522650

DO - 10.1109/IPEC.2012.6522650

M3 - Paper

AN - SCOPUS:84881047279

SP - 161

EP - 164

T2 - 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012

Y2 - 12 November 2012 through 14 November 2012

ER -

A 40nm CMOS full asynchronous nano-watt SAR ADC with 98% leakage power reduction by boosted self power gating

Abstract

Other

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this