Abstract
This paper presents an ultra low power and ultra low voltage SAR ADC. Full asynchronous operation and boosted self power gating are proposed to improve conversion accuracy and reduce static leakage power. Test chip fabricated in 40nm CMOS process has successfully reduced leakage power by 98% and it performs ENOB of 8.2bit and consumes only 0.65nW with 0.1kS/s at 0.5V. The power consumption is scalable up to 4MS/s and power supply range from 0.4 to 0.7V. The best figure of merit (FoM) of 5.2fJ/conversion-step was obtained with 20kS/s at 0.5V.
Original language | English |
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Pages | 161-164 |
Number of pages | 4 |
DOIs | |
Publication status | Published - 2012 Dec 1 |
Event | 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 - Kobe, Japan Duration: 2012 Nov 12 → 2012 Nov 14 |
Other
Other | 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 |
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Country/Territory | Japan |
City | Kobe |
Period | 12/11/12 → 12/11/14 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering