A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors

Yasuhisa Shimazaki, Noriyuki Miura, Tadahiro Kuroda

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
    Original languageEnglish
    Title of host publicationSymposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV
    DOIs
    Publication statusPublished - 2012 Jul 25
    Event15th IEEE Symposium on Low-Powerand High-Speed Chips, COOL Chips XV - Yokohama, Japan
    Duration: 2012 Apr 182012 Apr 20

    Publication series

    NameSymposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV

    Other

    Other15th IEEE Symposium on Low-Powerand High-Speed Chips, COOL Chips XV
    CountryJapan
    CityYokohama
    Period12/4/1812/4/20

    ASJC Scopus subject areas

    • Computer Networks and Communications

    Cite this

    Shimazaki, Y., Miura, N., & Kuroda, T. (2012). A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors. In Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV [6216583] (Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV). https://doi.org/10.1109/COOLChips.2012.6216583