A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors

Yasuhisa Shimazaki, Noriyuki Miura, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)
Original languageEnglish
Title of host publicationSymposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV
DOIs
Publication statusPublished - 2012
Event15th IEEE Symposium on Low-Powerand High-Speed Chips, COOL Chips XV - Yokohama, Japan
Duration: 2012 Apr 18 → 2012 Apr 20

Other

Other15th IEEE Symposium on Low-Powerand High-Speed Chips, COOL Chips XV
CountryJapan
CityYokohama
Period12/4/18 → 12/4/20

ASJC Scopus subject areas

  • Computer Networks and Communications

Cite this

Shimazaki, Y., Miura, N., & Kuroda, T. (2012). A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors. In Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV [6216583] https://doi.org/10.1109/COOLChips.2012.6216583

A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors. / Shimazaki, Yasuhisa; Miura, Noriyuki; Kuroda, Tadahiro.

Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV. 2012. 6216583.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Shimazaki, Y, Miura, N & Kuroda, T 2012, A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors. in Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV., 6216583, 15th IEEE Symposium on Low-Powerand High-Speed Chips, COOL Chips XV, Yokohama, Japan, 12/4/18. https://doi.org/10.1109/COOLChips.2012.6216583
Shimazaki Y, Miura N, Kuroda T. A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors. In Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV. 2012. 6216583 https://doi.org/10.1109/COOLChips.2012.6216583
Shimazaki, Yasuhisa ; Miura, Noriyuki ; Kuroda, Tadahiro. / A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors. Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV. 2012.
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