A 65 f J/b inductive-coupling inter-chip transceiver using charge recycling technique for power-aware 3d system integration

Kiichi Niitsu, Shusuke Kawai, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    10 Citations (Scopus)

    Abstract

    This paper discusses a low-power inductive-coupling link in 90 nm CMOS. The novel transmitter circuit using charge recycling technique for power-aware three-dimensional (3D) system integration is proposed and investigated. Cross-type daisy chain enables charge recycling and achieves power reduction while keeping communication performance such as high timing margin, low bit error rate and high bandwidth. There are two design issues in cross-type daisy, one is pulse amplitude reduction and another is inter-channel skew. To compensate them, inductor design and replica circuit is proposed and investigated. Test chips were designed and fabricated in 90nm CMOS to verify the proposed transmitter. Measured result showed that proposed cross-type daisy chain transmitter achieved an energy efficiency of 65 fj/bit without degrading any of timing margin, data rate and bit error rate.

    Original languageEnglish
    Title of host publicationProceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
    Pages97-100
    Number of pages4
    DOIs
    Publication statusPublished - 2008 Dec 1
    Event2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 - Fukuoka, Japan
    Duration: 2008 Nov 32008 Nov 5

    Publication series

    NameProceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008

    Other

    Other2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
    CountryJapan
    CityFukuoka
    Period08/11/308/11/5

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

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  • Cite this

    Niitsu, K., Kawai, S., Miura, N., Ishikuro, H., & Kuroda, T. (2008). A 65 f J/b inductive-coupling inter-chip transceiver using charge recycling technique for power-aware 3d system integration. In Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 (pp. 97-100). [4708738] (Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008). https://doi.org/10.1109/ASSCC.2008.4708738