A 65 f J/b inductive-coupling inter-chip transceiver using charge recycling technique for power-aware 3d system integration

Kiichi Niitsu; Shusuke Kawai; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda

doi:10.1109/ASSCC.2008.4708738

A 65 f J/b inductive-coupling inter-chip transceiver using charge recycling technique for power-aware 3d system integration

Kiichi Niitsu, Shusuke Kawai, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

14 Citations (Scopus)

Abstract

This paper discusses a low-power inductive-coupling link in 90 nm CMOS. The novel transmitter circuit using charge recycling technique for power-aware three-dimensional (3D) system integration is proposed and investigated. Cross-type daisy chain enables charge recycling and achieves power reduction while keeping communication performance such as high timing margin, low bit error rate and high bandwidth. There are two design issues in cross-type daisy, one is pulse amplitude reduction and another is inter-channel skew. To compensate them, inductor design and replica circuit is proposed and investigated. Test chips were designed and fabricated in 90nm CMOS to verify the proposed transmitter. Measured result showed that proposed cross-type daisy chain transmitter achieved an energy efficiency of 65 fj/bit without degrading any of timing margin, data rate and bit error rate.

Original language	English
Title of host publication	Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
Pages	97-100
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2008.4708738
Publication status	Published - 2008 Dec 1
Event	2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 - Fukuoka, Japan Duration: 2008 Nov 3 → 2008 Nov 5

Publication series

Name	Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008

Other

Other	2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
Country/Territory	Japan
City	Fukuoka
Period	08/11/3 → 08/11/5

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/ASSCC.2008.4708738

Cite this

Niitsu, K., Kawai, S., Miura, N., Ishikuro, H., & Kuroda, T. (2008). A 65 f J/b inductive-coupling inter-chip transceiver using charge recycling technique for power-aware 3d system integration. In Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 (pp. 97-100). [4708738] (Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008). https://doi.org/10.1109/ASSCC.2008.4708738

A 65 f J/b inductive-coupling inter-chip transceiver using charge recycling technique for power-aware 3d system integration. / Niitsu, Kiichi; Kawai, Shusuke; Miura, Noriyuki et al.
Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008. 2008. p. 97-100 4708738 (Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Niitsu, K, Kawai, S, Miura, N, Ishikuro, H & Kuroda, T 2008, A 65 f J/b inductive-coupling inter-chip transceiver using charge recycling technique for power-aware 3d system integration. in Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008., 4708738, Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008, pp. 97-100, 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008, Fukuoka, Japan, 08/11/3. https://doi.org/10.1109/ASSCC.2008.4708738

Niitsu K, Kawai S, Miura N, Ishikuro H, Kuroda T. A 65 f J/b inductive-coupling inter-chip transceiver using charge recycling technique for power-aware 3d system integration. In Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008. 2008. p. 97-100. 4708738. (Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008). doi: 10.1109/ASSCC.2008.4708738

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title = "A 65 f J/b inductive-coupling inter-chip transceiver using charge recycling technique for power-aware 3d system integration",

abstract = "This paper discusses a low-power inductive-coupling link in 90 nm CMOS. The novel transmitter circuit using charge recycling technique for power-aware three-dimensional (3D) system integration is proposed and investigated. Cross-type daisy chain enables charge recycling and achieves power reduction while keeping communication performance such as high timing margin, low bit error rate and high bandwidth. There are two design issues in cross-type daisy, one is pulse amplitude reduction and another is inter-channel skew. To compensate them, inductor design and replica circuit is proposed and investigated. Test chips were designed and fabricated in 90nm CMOS to verify the proposed transmitter. Measured result showed that proposed cross-type daisy chain transmitter achieved an energy efficiency of 65 fj/bit without degrading any of timing margin, data rate and bit error rate.",

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AU - Kuroda, Tadahiro

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N2 - This paper discusses a low-power inductive-coupling link in 90 nm CMOS. The novel transmitter circuit using charge recycling technique for power-aware three-dimensional (3D) system integration is proposed and investigated. Cross-type daisy chain enables charge recycling and achieves power reduction while keeping communication performance such as high timing margin, low bit error rate and high bandwidth. There are two design issues in cross-type daisy, one is pulse amplitude reduction and another is inter-channel skew. To compensate them, inductor design and replica circuit is proposed and investigated. Test chips were designed and fabricated in 90nm CMOS to verify the proposed transmitter. Measured result showed that proposed cross-type daisy chain transmitter achieved an energy efficiency of 65 fj/bit without degrading any of timing margin, data rate and bit error rate.

AB - This paper discusses a low-power inductive-coupling link in 90 nm CMOS. The novel transmitter circuit using charge recycling technique for power-aware three-dimensional (3D) system integration is proposed and investigated. Cross-type daisy chain enables charge recycling and achieves power reduction while keeping communication performance such as high timing margin, low bit error rate and high bandwidth. There are two design issues in cross-type daisy, one is pulse amplitude reduction and another is inter-channel skew. To compensate them, inductor design and replica circuit is proposed and investigated. Test chips were designed and fabricated in 90nm CMOS to verify the proposed transmitter. Measured result showed that proposed cross-type daisy chain transmitter achieved an energy efficiency of 65 fj/bit without degrading any of timing margin, data rate and bit error rate.

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A 65 f J/b inductive-coupling inter-chip transceiver using charge recycling technique for power-aware 3d system integration

Abstract

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ASJC Scopus subject areas

UN SDGs

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