A 65fJ/b inter-chip inductive-coupling data transceivers using charge-recycling technique for low-power inter-chip communication in 3-D system integration

Kiichi Niitsu, Shusuke Kawai, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda

Research output: Contribution to journalArticle

10 Citations (Scopus)

Abstract

This paper presents a low-power inductive-coupling link in 90-nm CMOS. Our newly proposed transmitter circuit uses a charge-recycling technique for power-aware 3-D system integration. The cross-type daisy chain enables charge recycling and achieves power reduction without sacrificing communication performance such as a high timing margin, low bit error rate and high bandwidth. There are two design issues in the cross-type daisy chain: pulse amplitude reduction and another is inter-channel skew. To compensate for these issues, an inductor design and a replica circuit are proposed and investigated. Test chips were designed and fabricated in 90-nm CMOS to verify the validity of the proposed transmitter. Measurements revealed that the proposed cross-type daisy chain transmitter achieved an energy efficiency of 65 fJ/bit without degrading the timing margin, data rate, or bit error rate. In order to investigate the compatibility of the transmitter with technology scaling, a simulation of each technology node was performed. The simulation results indicate that the energy dissipation can be potentially reduced to less than 10 fJ/bit in 22 nm CMOS with proposed cross-type daisy chain.

Original languageEnglish
Article number5887438
Pages (from-to)1285-1294
Number of pages10
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume20
Issue number7
DOIs
Publication statusPublished - 2012 Jan 1

    Fingerprint

Keywords

  • CMOS integrated circuits (ICs)
  • low-power design
  • wireless communication

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this