Abstract
Processor systems that are mounted in satellites must be small and light, having high data transfer rates, and high storage capacity [1]. A small reduction in size and weight could reduce the cost of launching a satellite by a significant amount. The next generation of earth observation satellites will require data transmission rates to a maximum of 20Gb/s and at least one terabyte of storage capacity. The volume, weight, and communication speed of the processor system is determined by the backplane connectors (Fig. 20.4.1). It is difficult to achieve a connector that can pass signals of 2.5Gb/s or more. The signal reflection that occurs when signals are branched at connectors and at the wire stubs of branches decreases the transmission speed, so only point-to-point connections are possible. Once the satellite is launched, repair or replacement is not possible, and system redundancy is introduced. Accordingly, 512 backplane wires would be required. The signal connector would require 1,024pins, including the ground pins used to prevent crosstalk, and would be 512mm wide, which is even wider than the circuit board of each module.
Original language | English |
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Title of host publication | Digest of Technical Papers - IEEE International Solid-State Circuits Conference |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 434-435 |
Number of pages | 2 |
Volume | 58 |
ISBN (Print) | 9781479962235 |
DOIs | |
Publication status | Published - 2015 Mar 17 |
Event | 2015 62nd IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers - San Francisco, United States Duration: 2015 Feb 22 → 2015 Feb 26 |
Other
Other | 2015 62nd IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers |
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Country | United States |
City | San Francisco |
Period | 15/2/22 → 15/2/26 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials