A 720μW 873MHz-1.008GHz injection-locked frequency multiplier with 0.3V supply voltage in 90nm CMOS

Lechang Liu; Keisuke Ishikawa; Tadahiro Kuroda

A 720μW 873MHz-1.008GHz injection-locked frequency multiplier with 0.3V supply voltage in 90nm CMOS

Lechang Liu, Keisuke Ishikawa, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A 0.3V parametric resonance based sub-GHz injection-locked frequency multiplier is developed in 90nm CMOS. This is the first reported variation-tolerant frequency multiplier with 0.3V supply voltage. It achieves 720μW power consumption and -110dBc@600kHz phase noise with the lowest supply voltage in state-of-the-art frequency synthesizers.

Original language	English
Title of host publication	2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers
Pages	C140-C141
Publication status	Published - 2013 Sept 17
Event	2013 Symposium on VLSI Circuits, VLSIC 2013 - Kyoto, Japan Duration: 2013 Jun 12 → 2013 Jun 14

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	2013 Symposium on VLSI Circuits, VLSIC 2013
Country/Territory	Japan
City	Kyoto
Period	13/6/12 → 13/6/14

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

A 720μW 873MHz-1.008GHz injection-locked frequency multiplier with 0.3V supply voltage in 90nm CMOS. / Liu, Lechang; Ishikawa, Keisuke; Kuroda, Tadahiro.

2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers. 2013. p. C140-C141 6578639 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Liu, L, Ishikawa, K & Kuroda, T 2013, A 720μW 873MHz-1.008GHz injection-locked frequency multiplier with 0.3V supply voltage in 90nm CMOS. in 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers., 6578639, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. C140-C141, 2013 Symposium on VLSI Circuits, VLSIC 2013, Kyoto, Japan, 13/6/12.

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abstract = "A 0.3V parametric resonance based sub-GHz injection-locked frequency multiplier is developed in 90nm CMOS. This is the first reported variation-tolerant frequency multiplier with 0.3V supply voltage. It achieves 720μW power consumption and -110dBc@600kHz phase noise with the lowest supply voltage in state-of-the-art frequency synthesizers.",

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A 720μW 873MHz-1.008GHz injection-locked frequency multiplier with 0.3V supply voltage in 90nm CMOS

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