A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line

Won Joo Yun, Shinya Nakano, Wataru Mizuhara, Atsutake Kosuge, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    17 Citations (Scopus)

    Abstract

    As computing power and speed increases, the demand for higher memory bandwidth increases as well. Recently, the memory interface has been improved up to 20Gb/s/link [1]. Considering PCB routing area, a multi-drop bus architecture is still preferable for large memory capacity to the point-to-point connection. However, the multi-drop approach suffers from performance degradations due to reflections at each stub. To mitigate this problem, reference [2] proposes an impedance-matched bidirectional multi-drop DQ bus architecture that is difficult to realize due to smaller series resistor if more than 4 modules are used. To avoid multi-reflections from each stub, other approaches have used coupled transmission lines (CTL) [3, 4]. While a horizontal directional coupler buried in the PCB was used [3], coupled traces on the bent loop of flex fixed to a module were used for signal delivery in vertical direction [4]. In [3], a long coupler with long main bus line was used so that the signal integrity degrades at the far-end coupler. In [4], the coupling traces on the motherboard and the flex have zigzag geometries for better misalignment tolerance, which result in large area of routing due to the minimum required pitch between traces. In [5], the CTL needs to be placed close to a Tx/Rx chip, as there are no extended transmission lines for signal lead. Therefore, it cannot be used for memory modules. DRAM multi-drop bus interface technology mapping is described in Fig. 2.8.1.

    Original languageEnglish
    Title of host publication2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers
    Pages52-53
    Number of pages2
    DOIs
    Publication statusPublished - 2012 May 11
    Event59th International Solid-State Circuits Conference, ISSCC 2012 - San Francisco, CA, United States
    Duration: 2012 Feb 192012 Feb 23

    Publication series

    NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
    Volume55
    ISSN (Print)0193-6530

    Other

    Other59th International Solid-State Circuits Conference, ISSCC 2012
    CountryUnited States
    CitySan Francisco, CA
    Period12/2/1912/2/23

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering

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  • Cite this

    Yun, W. J., Nakano, S., Mizuhara, W., Kosuge, A., Miura, N., Ishikuro, H., & Kuroda, T. (2012). A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line. In 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers (pp. 52-53). [6176875] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 55). https://doi.org/10.1109/ISSCC.2012.6176875