A 9-bit 100MS/s SAR ADC with digitally assisted background calibration

Xiaolei Zhu, Yanfei Chen, Sanroku Tsukamoto, Tadahiro Kuroda

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

The performance of successive approximation register (SAR) analog-to-digital converter (ADC) is well balanced between power and speed compare to the conventional flash or pipeline architecture. The nonlinearities suffer from the CDAC mismatch and comparator offset degrades SAR ADC performance in terms of DNL and INL. An on chip histogram-based digitally assisted background calibration technique is proposed to cancel and relax the aforesaid nonlinearities. The calibration is performed using the input signal, watching the digital codes in the specified vicinity of the decision boundaries, and feeding back to control the compensation capacitor periodically. The calibration does not require special calibration signal or additional analog hardware which is simple and amenable to hardware or software implementations. A 9-bit SAR ADC with split CDAC has been implemented in a 65 nm CMOS technology and it achieves a peak SNDR of 50.81 dB and consumes 1.34mW from a 1.2-V supply. +0.4/-0.4 LSB DNL and +0.5/-0.7 LSB INL are achieved after calibration. The ADC has input capacitance of 180 fF and occupies an area of 0.1 ×0.13mm 2.

Original languageEnglish
Pages (from-to)1026-1034
Number of pages9
JournalIEICE Transactions on Electronics
VolumeE95-C
Issue number6
DOIs
Publication statusPublished - 2012 Jun

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Digital to analog conversion
Calibration
Hardware
Capacitors
Capacitance
Pipelines
chlorambucil-docosahexaenoic acid conjugate

Keywords

  • ADC
  • Charge redistribution
  • Digital background calibration
  • Nonlinearity
  • Split capacitor DAC
  • Successive approximation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

A 9-bit 100MS/s SAR ADC with digitally assisted background calibration. / Zhu, Xiaolei; Chen, Yanfei; Tsukamoto, Sanroku; Kuroda, Tadahiro.

In: IEICE Transactions on Electronics, Vol. E95-C, No. 6, 06.2012, p. 1026-1034.

Research output: Contribution to journalArticle

Zhu, Xiaolei ; Chen, Yanfei ; Tsukamoto, Sanroku ; Kuroda, Tadahiro. / A 9-bit 100MS/s SAR ADC with digitally assisted background calibration. In: IEICE Transactions on Electronics. 2012 ; Vol. E95-C, No. 6. pp. 1026-1034.
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