A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array

Xiaolei Zhu, Yanfei Chen, Sanroku Tsukamoto, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

The capacitor digital-to-analog converter (CDAC) which affects the system performance of speed and linearity occupies the most area in successive approximation register (SAR) analog-to-digital converter (ADC). The performance of tri-level SAR ADC is well balanced between power and speed comparing to the conventional CDAC based architecture. In order to further improve the ADC performance in light of area and energy efficiencies, a partially asymmetric tri-level CDAC design technique is proposed to save the silicon cost and power as well. Combining the asymmetric CDAC approach with the tri-level charge redistribution technique makes it possible for the SAR ADC to achieve a 9-bit resolution with 4-bit + 3-bit split capacitor arrays. A 9-bit SAR ADC with CDAC calibration has been implemented in a 65nm CMOS technology and it achieves a peak SNDR of 50.1 dB and consumes 1.26 mW from a 1.2-V supply, corresponding to a FOM of 45fJ/conv.-step. The static performance of +0.4/0.5 LSB DNL and +0.5/0.7 LSB INL is achieved. The ADC has input capacitance of 180 fF and occupies an active area of 0.10.13 mm 2.

Original languageEnglish
Title of host publication2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers
DOIs
Publication statusPublished - 2012
Event2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Hsinchu, Taiwan, Province of China
Duration: 2012 Apr 232012 Apr 25

Other

Other2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012
CountryTaiwan, Province of China
CityHsinchu
Period12/4/2312/4/25

Fingerprint

Digital to analog conversion
Capacitors
Energy efficiency
Capacitance
Calibration
Silicon

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Zhu, X., Chen, Y., Tsukamoto, S., & Kuroda, T. (2012). A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array. In 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers [6212592] https://doi.org/10.1109/VLSI-DAT.2012.6212592

A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array. / Zhu, Xiaolei; Chen, Yanfei; Tsukamoto, Sanroku; Kuroda, Tadahiro.

2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 2012. 6212592.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Zhu, X, Chen, Y, Tsukamoto, S & Kuroda, T 2012, A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array. in 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers., 6212592, 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012, Hsinchu, Taiwan, Province of China, 12/4/23. https://doi.org/10.1109/VLSI-DAT.2012.6212592
Zhu X, Chen Y, Tsukamoto S, Kuroda T. A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array. In 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 2012. 6212592 https://doi.org/10.1109/VLSI-DAT.2012.6212592
Zhu, Xiaolei ; Chen, Yanfei ; Tsukamoto, Sanroku ; Kuroda, Tadahiro. / A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array. 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 2012.
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