A case for random shortcut topologies for HPC interconnects

Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, D. Frank Hsu, Henri Casanova

Research output: Chapter in Book/Report/Conference proceedingConference contribution

75 Citations (Scopus)

Abstract

As the scales of parallel applications and platforms increase the negative impact of communication latencies on performance becomes large. Fortunately, modern High Performance Computing (HPC) systems can exploit low-latency topologies of high-radix switches. In this context, we propose the use of random shortcut topologies, which are generated by augmenting classical topologies with random links. Using graph analysis we find that these topologies, when compared to non-random topologies of the same degree, lead to drastically reduced diameter and average shortest path length. The best results are obtained when adding random links to a ring topology, meaning that good random shortcut topologies can easily be generated for arbitrary numbers of switches. Using flit-level discrete event simulation we find that random shortcut topologies achieve throughput comparable to and latency lower than that of existing non-random topologies such as hypercubes and tori. Finally, we discuss and quantify practical challenges for random shortcut topologies, including routing scalability and larger physical cable lengths.

Original languageEnglish
Title of host publicationProceedings - International Symposium on Computer Architecture
Pages177-188
Number of pages12
DOIs
Publication statusPublished - 2012
Event2012 39th Annual International Symposium on Computer Architecture, ISCA 2012 - Portland, OR, United States
Duration: 2012 Jun 92012 Jun 13

Other

Other2012 39th Annual International Symposium on Computer Architecture, ISCA 2012
CountryUnited States
CityPortland, OR
Period12/6/912/6/13

Fingerprint

Topology
Switches
Discrete event simulation
Scalability
Cables
Throughput
Communication

Keywords

  • diameter
  • high performance computing
  • high-radix switches
  • interconnection networks
  • Topology

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Koibuchi, M., Matsutani, H., Amano, H., Hsu, D. F., & Casanova, H. (2012). A case for random shortcut topologies for HPC interconnects. In Proceedings - International Symposium on Computer Architecture (pp. 177-188). [6237016] https://doi.org/10.1109/ISCA.2012.6237016

A case for random shortcut topologies for HPC interconnects. / Koibuchi, Michihiro; Matsutani, Hiroki; Amano, Hideharu; Hsu, D. Frank; Casanova, Henri.

Proceedings - International Symposium on Computer Architecture. 2012. p. 177-188 6237016.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Koibuchi, M, Matsutani, H, Amano, H, Hsu, DF & Casanova, H 2012, A case for random shortcut topologies for HPC interconnects. in Proceedings - International Symposium on Computer Architecture., 6237016, pp. 177-188, 2012 39th Annual International Symposium on Computer Architecture, ISCA 2012, Portland, OR, United States, 12/6/9. https://doi.org/10.1109/ISCA.2012.6237016
Koibuchi M, Matsutani H, Amano H, Hsu DF, Casanova H. A case for random shortcut topologies for HPC interconnects. In Proceedings - International Symposium on Computer Architecture. 2012. p. 177-188. 6237016 https://doi.org/10.1109/ISCA.2012.6237016
Koibuchi, Michihiro ; Matsutani, Hiroki ; Amano, Hideharu ; Hsu, D. Frank ; Casanova, Henri. / A case for random shortcut topologies for HPC interconnects. Proceedings - International Symposium on Computer Architecture. 2012. pp. 177-188
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