A Circuit Design for 2-Gbit/s Si Bipolar Crosspoint Switch LSI’s

Masao Suzuki, Michihiro Hirata, Naoaki Yamanaka, Shiro Kikuchi

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

— A Si bipolar circuit design technology for gigabit-per-second crosspoint switch LSI’s is described. An 8×8 and an expandable 16X 16 crosspoint switch LSI have been developed utilizing a new circuit design and super self-aligned process technology (SST-1A). The LSI’s successfully switched with a bit error rate of less than 10-9 at 2.5 Gbit/s using a 29 - 1 pseudorandom NRZ sequence. Pulse jitter has been limited to less than 80 ps at 1.2 Gbit/s by utilizing a small internal voltage swing (225 mV) employing a differential CML cell, including a selector. The LSI’s have an ECL-compatible interface, -4- and -2-V power supply voltages, and a power dissipation of less than 0.9 W for the 8 X 8 LSI and 2.8 W for the expandable 16 ×16 LSI.

Original languageEnglish
Pages (from-to)155-159
Number of pages5
JournalIEEE Journal of Solid-State Circuits
Volume25
Issue number1
DOIs
Publication statusPublished - 1990 Feb
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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