A circuit division method for high-level synthesis on multi-FPGA systems

Kugami Daiki, Takaaki Miyajima, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

High-Level Synthesis has been researched and developed for these 20 years. Not only ASIC, but also reconfigurable devices, especially Field Programmable Gate Array (FPGA) development environment has been improved as well. Various types of large algorithms also have been implemented on FPGAs in order to shorten their processing time, especially in the field of Computational Fluid Dynamics(CFD). However, for such an acceleration, FPGA has some limitations when programmers try to implement large algorithm. Area is one of the largest constraints for FPGA, so programmers have to divide one large algorithm into some small parts. The number of arithmetic units also constraints the size of algorithm and degree of the speed-up. Here, wetry to divide a large algorithm into some small functions, and implement on some FPGAs by using a High-Level Synthesis(HLS) tool. Since the trial and error is easy to be done withHLS tool, we propose a technique for exploration of division point of a large algorithm by using a HLS tool CWB (Cyber Work Bench).

Original languageEnglish
Title of host publicationProceedings - 27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013
Pages156-161
Number of pages6
DOIs
Publication statusPublished - 2013
Event27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013 - Barcelona, Spain
Duration: 2013 Mar 252013 Mar 28

Other

Other27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013
CountrySpain
CityBarcelona
Period13/3/2513/3/28

Fingerprint

Field programmable gate arrays (FPGA)
Networks (circuits)
Application specific integrated circuits
High level synthesis
Computational fluid dynamics
Processing

Keywords

  • Circuit Division
  • High Level Synthesis
  • HLS
  • Loop Unrolling
  • Multi FPGA

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Computer Science Applications

Cite this

Daiki, K., Miyajima, T., & Amano, H. (2013). A circuit division method for high-level synthesis on multi-FPGA systems. In Proceedings - 27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013 (pp. 156-161). [6550389] https://doi.org/10.1109/WAINA.2013.266

A circuit division method for high-level synthesis on multi-FPGA systems. / Daiki, Kugami; Miyajima, Takaaki; Amano, Hideharu.

Proceedings - 27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013. 2013. p. 156-161 6550389.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Daiki, K, Miyajima, T & Amano, H 2013, A circuit division method for high-level synthesis on multi-FPGA systems. in Proceedings - 27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013., 6550389, pp. 156-161, 27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013, Barcelona, Spain, 13/3/25. https://doi.org/10.1109/WAINA.2013.266
Daiki K, Miyajima T, Amano H. A circuit division method for high-level synthesis on multi-FPGA systems. In Proceedings - 27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013. 2013. p. 156-161. 6550389 https://doi.org/10.1109/WAINA.2013.266
Daiki, Kugami ; Miyajima, Takaaki ; Amano, Hideharu. / A circuit division method for high-level synthesis on multi-FPGA systems. Proceedings - 27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013. 2013. pp. 156-161
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