A circuit division method for high-level synthesis on multi-FPGA systems

High-Level Synthesis has been researched and developed for these 20 years. Not only ASIC, but also reconfigurable devices, especially Field Programmable Gate Array (FPGA) development environment has been improved as well. Various types of large algorithms also have been implemented on FPGAs in order to shorten their processing time, especially in the field of Computational Fluid Dynamics(CFD). However, for such an acceleration, FPGA has some limitations when programmers try to implement large algorithm. Area is one of the largest constraints for FPGA, so programmers have to divide one large algorithm into some small parts. The number of arithmetic units also constraints the size of algorithm and degree of the speed-up. Here, wetry to divide a large algorithm into some small functions, and implement on some FPGAs by using a High-Level Synthesis(HLS) tool. Since the trial and error is easy to be done withHLS tool, we propose a technique for exploration of division point of a large algorithm by using a HLS tool CWB (Cyber Work Bench).