Abstract
High-Level Synthesis has been researched and developed for these 20 years. Not only ASIC, but also reconfigurable devices, especially Field Programmable Gate Array (FPGA) development environment has been improved as well. Various types of large algorithms also have been implemented on FPGAs in order to shorten their processing time, especially in the field of Computational Fluid Dynamics(CFD). However, for such an acceleration, FPGA has some limitations when programmers try to implement large algorithm. Area is one of the largest constraints for FPGA, so programmers have to divide one large algorithm into some small parts. The number of arithmetic units also constraints the size of algorithm and degree of the speed-up. Here, wetry to divide a large algorithm into some small functions, and implement on some FPGAs by using a High-Level Synthesis(HLS) tool. Since the trial and error is easy to be done withHLS tool, we propose a technique for exploration of division point of a large algorithm by using a HLS tool CWB (Cyber Work Bench).
| Original language | English |
|---|---|
| Title of host publication | Proceedings - 27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013 |
| Pages | 156-161 |
| Number of pages | 6 |
| DOIs | |
| Publication status | Published - 2013 |
| Event | 27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013 - Barcelona, Spain Duration: 2013 Mar 25 → 2013 Mar 28 |
Other
| Other | 27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013 |
|---|---|
| Country | Spain |
| City | Barcelona |
| Period | 13/3/25 → 13/3/28 |
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Keywords
- Circuit Division
- High Level Synthesis
- HLS
- Loop Unrolling
- Multi FPGA
ASJC Scopus subject areas
- Computer Networks and Communications
- Computer Science Applications
Cite this
A circuit division method for high-level synthesis on multi-FPGA systems. / Daiki, Kugami; Miyajima, Takaaki; Amano, Hideharu.
Proceedings - 27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013. 2013. p. 156-161 6550389.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - A circuit division method for high-level synthesis on multi-FPGA systems
AU - Daiki, Kugami
AU - Miyajima, Takaaki
AU - Amano, Hideharu
PY - 2013
Y1 - 2013
N2 - High-Level Synthesis has been researched and developed for these 20 years. Not only ASIC, but also reconfigurable devices, especially Field Programmable Gate Array (FPGA) development environment has been improved as well. Various types of large algorithms also have been implemented on FPGAs in order to shorten their processing time, especially in the field of Computational Fluid Dynamics(CFD). However, for such an acceleration, FPGA has some limitations when programmers try to implement large algorithm. Area is one of the largest constraints for FPGA, so programmers have to divide one large algorithm into some small parts. The number of arithmetic units also constraints the size of algorithm and degree of the speed-up. Here, wetry to divide a large algorithm into some small functions, and implement on some FPGAs by using a High-Level Synthesis(HLS) tool. Since the trial and error is easy to be done withHLS tool, we propose a technique for exploration of division point of a large algorithm by using a HLS tool CWB (Cyber Work Bench).
AB - High-Level Synthesis has been researched and developed for these 20 years. Not only ASIC, but also reconfigurable devices, especially Field Programmable Gate Array (FPGA) development environment has been improved as well. Various types of large algorithms also have been implemented on FPGAs in order to shorten their processing time, especially in the field of Computational Fluid Dynamics(CFD). However, for such an acceleration, FPGA has some limitations when programmers try to implement large algorithm. Area is one of the largest constraints for FPGA, so programmers have to divide one large algorithm into some small parts. The number of arithmetic units also constraints the size of algorithm and degree of the speed-up. Here, wetry to divide a large algorithm into some small functions, and implement on some FPGAs by using a High-Level Synthesis(HLS) tool. Since the trial and error is easy to be done withHLS tool, we propose a technique for exploration of division point of a large algorithm by using a HLS tool CWB (Cyber Work Bench).
KW - Circuit Division
KW - High Level Synthesis
KW - HLS
KW - Loop Unrolling
KW - Multi FPGA
UR - http://www.scopus.com/inward/record.url?scp=84881426481&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84881426481&partnerID=8YFLogxK
U2 - 10.1109/WAINA.2013.266
DO - 10.1109/WAINA.2013.266
M3 - Conference contribution
AN - SCOPUS:84881426481
SN - 9780769549521
SP - 156
EP - 161
BT - Proceedings - 27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013
ER -